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1. 发明授权

US08474104B2 Cable tie 失效
标题翻译：电缆扎带
公开(公告)号：US08474104B2
公开(公告)日：2013-07-02
申请号：US13054196
申请日：2009-07-06
申请人： Robert Baird Watson
发明人： Robert Baird Watson
IPC分类号： B65D63/10
CPC分类号： B65D63/1063 , F16L3/2336 , H02G3/30 , Y10T24/14 , Y10T24/1498
摘要： A binding head and binding arrangement that cooperates with an elongate member that has a fastening end and a locking end. The fastening end is spaced apart from the locking end along the length of the elongate member and each elongate member has at least one lengthwise side that includes at least two teeth. The binding head includes a fastening opening for receiving a fastening end of an elongate member. The fastening opening includes a first fastening arrangement configured to cooperate with at least one of the teeth of the elongate member to lock a portion of the elongate member within the fastening opening; and a locking opening for receiving a locking end of an elongate member. The locking opening includes a second fastening arrangement configured to cooperate with at least one of the teeth of the elongate member to lock a portion of the elongate member within the locking opening. A cable tie is also claimed which includes the binding head and binding arrangement.
摘要翻译：与具有紧固端和锁定端的细长构件配合的装订头和装订装置。紧固端沿着细长构件的长度与锁定端隔开，并且每个细长构件具有包括至少两个齿的至少一个纵向侧。装订头包括用于接收细长构件的紧固端的紧固开口。紧固开口包括第一紧固装置，其被配置为与细长构件的至少一个齿配合以将细长构件的一部分锁定在紧固开口内; 以及用于接收细长构件的锁定端的锁定开口。锁定开口包括第二紧固装置，其被配置为与细长构件的至少一个齿配合以将细长构件的一部分锁定在锁定开口内。还要求一种包括装订头和装订装置的电缆扎带。

2. 发明申请

US20110131768A1 CABLE TIE 失效
标题翻译：电缆线
公开(公告)号：US20110131768A1
公开(公告)日：2011-06-09
申请号：US13054196
申请日：2009-07-06
申请人： Robert Baird Watson
发明人： Robert Baird Watson
IPC分类号： B65D63/14 , B65D63/00
CPC分类号： B65D63/1063 , F16L3/2336 , H02G3/30 , Y10T24/14 , Y10T24/1498
摘要： A binding head and binding arrangement that cooperates with an elongate member that has a fastening end and a locking end. The fastening end is spaced apart from the locking end along the length of the elongate member and each elongate member has at least one lengthwise side that includes at least two teeth. The binding head includes a fastening opening for receiving a fastening end of an elongate member. The fastening opening includes a first fastening arrangement configured to cooperate with at least one of the teeth of the elongate member to lock a portion of the elongate member within the fastening opening; and a locking opening for receiving a locking end of an elongate member. The locking opening includes a second fastening arrangement configured to cooperate with at least one of the teeth of the elongate member to lock a portion of the elongate member within the locking opening. A cable tie is also claimed which includes the binding head and binding arrangement.
摘要翻译：与具有紧固端和锁定端的细长构件配合的装订头和装订装置。紧固端沿着细长构件的长度与锁定端隔开，并且每个细长构件具有包括至少两个齿的至少一个纵向侧。装订头包括用于接收细长构件的紧固端的紧固开口。紧固开口包括第一紧固装置，其被配置为与细长构件的至少一个齿配合以将细长构件的一部分锁定在紧固开口内; 以及用于接收细长构件的锁定端的锁定开口。锁定开口包括第二紧固装置，其被配置为与细长构件的至少一个齿配合以将细长构件的一部分锁定在锁定开口内。还要求一种包括装订头和装订装置的电缆扎带。

3. 发明申请

US20070076330A1 Magnetic tunnel junction temperature sensors 失效
标题翻译：磁隧道结温度传感器
公开(公告)号：US20070076330A1
公开(公告)日：2007-04-05
申请号：US11240514
申请日：2005-09-30
申请人： Young Chung , Robert Baird , Mark Durlam
发明人： Young Chung , Robert Baird , Mark Durlam
IPC分类号： G11B5/33
CPC分类号： G11C11/16 , G01K7/01 , G11C29/50 , G11C29/50008 , G11C2029/5002
摘要： An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.
摘要翻译：提供一种集成电路装置，其包括设置在基板中的热源和设置在热源上方的磁隧道结（“MTJ”）温度传感器。

4. 发明申请

US20070045759A1 Passive elements in MRAM embedded integrated circuits 有权
公开(公告)号：US20070045759A1
公开(公告)日：2007-03-01
申请号：US11217146
申请日：2005-08-31
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： H01L43/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

5. 发明申请

US20070002609A1 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US20070002609A1
公开(公告)日：2007-01-04
申请号：US11170874
申请日：2005-06-30
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： G11C11/14
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

6. 发明申请

US20060226509A1 Antifuse element and electrically redundant antifuse array for controlled rupture location 有权
标题翻译：防腐元件和电气冗余反熔丝阵列，用于受控断裂位置
公开(公告)号：US20060226509A1
公开(公告)日：2006-10-12
申请号：US11095302
申请日：2005-03-31
申请人： Won Min , Robert Baird , Jiang-Kai Zuo , Gordon Lee
发明人： Won Min , Robert Baird , Jiang-Kai Zuo , Gordon Lee
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The high electric field created at the end corners (120, 122) of the gate electrode (104) results in a breakdown and rupture of the insulating layer (110) at points directly beneath the end corners (120, 122). This localization of the insulating layer (110) at the corners (120,122) provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements (102) when integrated into an array (300, 320, 400, 550) provide for increased packing density. The array is fabricated to include multiple active areas (304) for individual antifuse element (302) programming or a common active area (324,405,426,506) for multi-element programming.
摘要翻译：具有位于有源区域（106）或底部电极正上方的栅电极（104）的端角（120,122）的反熔断元件（102）。栅电极（104）和有源区（106）之间的最小编程电压产生通过位于它们之间的绝缘层（110）的电流路径。在栅电极（104）的端角（120,122）处产生的高电场导致在端角（120,122）正下方的绝缘层（110）的破裂和破裂。绝缘层（110）在拐角（120,122）处的定位提供较低的后编程电阻和变化，并且以较低的编程功率进行更快的编程。当反熔丝元件（102）集成到阵列（300,320,400,550）中时，提供了增加的堆积密度。阵列被制造为包括用于单个反熔丝元件（302）编程的多个有效区域（304）或用于多元件编程的公共有效区域（324,405,426,506）。

7. 发明申请

US20060003551A1 Ultra-thin die and method of fabricating same 有权
公开(公告)号：US20060003551A1
公开(公告)日：2006-01-05
申请号：US10881144
申请日：2004-06-30
申请人： David Mancini , Young Chung , William Dauksher , Donald Weston , Steven Young , Robert Baird
发明人： David Mancini , Young Chung , William Dauksher , Donald Weston , Steven Young , Robert Baird
IPC分类号： H01L21/301 , H01L21/46
CPC分类号： H01L21/3065 , H01L21/78 , Y10S438/977
摘要： In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

8. 发明授权

US5720460A Fixing clip 失效
标题翻译：固定夹
公开(公告)号：US5720460A
公开(公告)日：1998-02-24
申请号：US629559
申请日：1996-04-09
申请人： Robert Baird Watson
发明人： Robert Baird Watson
IPC分类号： E04B9/06 , E04F13/08 , A47F1/10
CPC分类号： E04B9/06 , E04F13/0816
摘要： A fixing clip for mounting a furring channel onto a support structure. The clip has a base portion through which the clip is attached to the support structure. A connection portion extends from the base portion so as to outstand from the support structure when the clip is attached thereto. A furring channel is connectable to the connection portion at a selected one of a plurality of connecting positions spaced from the base portion. That in turn locates the furring channel at a predetermined distance from the support structure.
摘要翻译：用于将毛边通道安装到支撑结构上的固定夹。夹子具有基部，夹子通过该基部附接到支撑结构。当夹子附接到其上时，连接部分从基部延伸以便从支撑结构突出。在与基部间隔开的多个连接位置中的选定的一个处，可以将连接部连接到连接部。这又将防护通道定位在离支撑结构预定距离处。

9. 发明申请

US20130145450A1 AUDITABLE MULTICLAIM SECURITY TOKEN 有权
标题翻译：可疑多元化安全措施
公开(公告)号：US20130145450A1
公开(公告)日：2013-06-06
申请号：US13310280
申请日：2011-12-02
申请人： Rosanne Gamble , Robert Baird
发明人： Rosanne Gamble , Robert Baird
IPC分类号： H04L9/32 , G06F21/00
CPC分类号： H04L63/0807
摘要： The current invention provides a paradigm for securely transmitting messages using an auditable message token and associated protocol for recording information pertaining to events occurring with respect to transmission(s) of a message.
摘要翻译：本发明提供了一种用于使用可审计消息令牌和相关联的协议来安全地传送消息的范例，用于记录与关于消息的传输发生的事件有关的信息。

10. 发明授权

US08401997B1 System and method for replication using consistency interval markers in a distributed storage environment 有权
标题翻译：在分布式存储环境中使用一致性间隔标记进行复制的系统和方法
公开(公告)号：US08401997B1
公开(公告)日：2013-03-19
申请号：US11230976
申请日：2005-09-20
申请人： Deepak Tawri , Ronald S. Karr , John A. Colgrove , Raghu Krishnamurthy , Anand A. Kekre , Robert Baird , Oleg Kiselev
发明人： Deepak Tawri , Ronald S. Karr , John A. Colgrove , Raghu Krishnamurthy , Anand A. Kekre , Robert Baird , Oleg Kiselev
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F11/2064 , G06F11/2071 , G06F2201/84 , G06F2201/855
摘要： Applications executing on various nodes in a distributed storage environment may write data to primary storage and may also replicate the data to secondary storage via a replication target. An interval coordinator may coordinate the periodic saving of checkpoints or snapshots of the replicated data. The interval coordinator may determine the length of consistency intervals between the saving of each of the checkpoints. Writes to the replication target from each of the nodes may be associated with the current consistency interval and, in some embodiments, with a unique per-node sequence number. When transitioning between consistency intervals, each node may be configured to temporarily suspend completion of the writes and to send the replication target a consistency interval marker indicating that the node has completed all writes for the current consistency interval.
摘要翻译：在分布式存储环境中在各种节点上执行的应用程序可以将数据写入主存储器，并且还可以经由复制目标将数据复制到辅助存储器。间隔协调器可以协调定期保存复制数据的检查点或快照。间隔协调器可以确定保存每个检查点之间的一致性间隔的长度。从每个节点写入复制目标可以与当前的一致性间隔相关联，并且在一些实施例中可以与唯一的每节点序列号相关联。当在一致性间隔之间转换时，可以将每个节点配置为临时挂起写入完成，并向复制目标发送指示节点已完成当前一致性间隔的所有写入的一致性间隔标记。

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