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1. 发明授权

US07489724B2 System and method for connecting a host and a target 有权
标题翻译：用于连接主机和目标的系统和方法
公开(公告)号：US07489724B2
公开(公告)日：2009-02-10
申请号：US10247263
申请日：2002-09-18
申请人： Robert Geoffrey Warren
发明人： Robert Geoffrey Warren
IPC分类号： H04B1/38
CPC分类号： G01R31/318552 , G01R31/31937
摘要： A system for controlling communications between a host and a target, the system having a data input for receiving a data signal, a clock input for receiving a clock signal, an oversampling circuit for sampling a received data signal and generating a control signal to control processing of the received data signal based at least in part on samples of the received data signal.
摘要翻译：一种用于控制主机和目标之间的通信的系统，具有用于接收数据信号的数据输入的系统，用于接收时钟信号的时钟输入，用于对接收的数据信号进行采样的过采样电路，并产生控制信号以控制处理至少部分地基于所接收的数据信号的样本。

2. 发明授权

US07839963B2 Isochronous synchronizer 有权
标题翻译：同步同步器
公开(公告)号：US07839963B2
公开(公告)日：2010-11-23
申请号：US11635384
申请日：2006-12-07
申请人： Robert Geoffrey Warren
发明人： Robert Geoffrey Warren
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Circuitry for synchronizing communications between clock environments wherein a change of state is transmitted from a first clock environment to a second clock environment, the first clock environment being timed by a first clock signal and the second clock environment being timed by a second clock signal, the first and second clock signals having nominally the same frequency but an unknown phase relationship, the circuitry comprising: delay means in the first clock environment arranged to generate a plurality of timing signals by delaying said first clock signal by respectively different delay values; sampling means in the second clock environment for sampling said plurality of timing signals at timing determined by said second clock signal thereby generating a plurality of sampled timing signals; and determining means for generating a control signal based on said plurality of sampled timing signals and outputting said control signal for controlling the transfer time of said change of state.
摘要翻译：电路，用于在其中将状态改变从第一时钟环境传输到第二时钟环境的时钟环境之间进行通信，所述第一时钟环境由第一时钟信号定时，并且所述第二时钟环境由第二时钟信号定时，第一和第二时钟信号具有名义上相同的频率但是未知的相位关系，所述电路包括：第一时钟环境中的延迟装置，被布置成通过分别延迟所述第一时钟信号分别不同的延迟值来产生多个定时信号; 在第二时钟环境中的采样装置，用于在由所述第二时钟信号确定的定时采样所述多个定时信号从而产生多个采样的定时信号; 以及确定装置，用于基于所述多个采样定时信号产生控制信号，并输出所述控制信号以控制所述状态改变的传送时间。

3. 发明授权

US07694264B2 Pulse link and apparatus for transmitting data and timing information on a single line 有权
标题翻译：用于在一条线路上发送数据和定时信息的脉冲链路和装置
公开(公告)号：US07694264B2
公开(公告)日：2010-04-06
申请号：US11635369
申请日：2006-12-07
申请人： Robert Geoffrey Warren
发明人： Robert Geoffrey Warren
IPC分类号： G06F17/50
CPC分类号： H04L25/4902 , H03K5/135 , H04Q2213/13034 , H04Q2213/13076 , H04Q2213/13213 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/1336
摘要： A routing block using a switch with a pulsed serial link. An input of a routing block is supplied with an information signal. The routing block has multiple outputs. The information signal includes a first edge and a second edge on a single line. The first and second edges are separated by a time period. One of the first and second edges represents information conveyed by the signal. The other one of the first and second edges provides timing information. The information signal controls the routing block to select one of the multiple outputs and the transferring the signal to said selected one of said multiple outputs. Depending on the number of bits of information transmitted in each pulse and the number of switches controlled by the control information, the decoded control data will include at least one bit outputted serially to a control signal generator block.
摘要翻译：使用带脉冲串行链路的交换机的路由块。向路由块的输入提供信息信号。路由块有多个输出。信息信号包括在一条线上的第一边缘和第二边缘。第一和第二边缘被分隔一段时间。第一和第二边中的一个表示由信号传送的信息。第一和第二边缘中的另一个提供定时信息。信息信号控制路由块以选择多个输出中的一个并将信号传送到所述多个输出中的所选择的一个。根据在每个脉冲中发送的信息的位数和由控制信息控制的开关的数量，解码的控制数据将包括串行地输出到控制信号发生器块的至少一个位。

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