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    • 2. 发明授权
    • System and method for supporting a server-side event model in a distributed data grid
    • 在分布式数据网格中支持服务器端事件模型的系统和方法
    • US09348668B2
    • 2016-05-24
    • US13462719
    • 2012-05-02
    • Brian OliverNoah ArlissGene GleyzerRobert H. Lee
    • Brian OliverNoah ArlissGene GleyzerRobert H. Lee
    • G06F9/46G06F9/54
    • H04L41/0631G06F9/542G06F17/30575G06F2209/542H04L67/1097H04L67/16H04L67/42
    • A server-side event model provides a general-purpose event framework which simplifies the server-side programming model in a distributed data grid storing data partitions distributed throughout a cluster of nodes. A system provides event interceptors which handle events associated with operations and maps the event interceptors to event dispatchers placed in the cluster. Advantageously, the system supports handling critical path events without the need for interactions from the client-side thereby avoiding unnecessary delays waiting for client responses. Additionally, the system can defer completion of an operation in the distributed data grid pending completion of event handling by an event interceptor. The system enables the data grid to employ more types of events and define different event interceptors for handling the events while avoiding client interaction overhead.
    • 服务器端事件模型提供了一个通用事件框架,它简化了分布式数据网格中的服务器端编程模型,从而存储分布在整个节点集群中的数据分区。 系统提供事件拦截器,其处理与操作相关联的事件,并将事件拦截器映射到放置在群集中的事件分派器。 有利地,系统支持处理关键路径事件,而不需要来自客户端的交互,从而避免等待客户端响应的不必要的延迟。 此外,系统可以延迟完成分布式数据网格中的操作,等待事件拦截器完成事件处理。 该系统使数据网格能够采用更多类型的事件,并定义不同的事件拦截器来处理事件,同时避免客户端的交互开销。
    • 3. 发明授权
    • Query explain plan in a distributed data management system
    • 在分布式数据管理系统中查询解释计划
    • US08868546B2
    • 2014-10-21
    • US13420324
    • 2012-03-14
    • Tom BeerbowerRobert H. Lee
    • Tom BeerbowerRobert H. Lee
    • G06F17/30G06F7/00
    • G06F17/30545G06F17/30433G06F17/30445G06F17/30463G06F17/30474G06F17/30595
    • A query explain plan is described for use with a distributed data system in order to help developers and IT experts to detect bottlenecks and to determine which queries are to blame for a slow running system. In accordance with an embodiment, the distributed data grid utilizes a facility to provide a distributed explain plan. This distributed explain plan provides visibility into how a query was answered by each node in the cluster. For example, one node may have applied the filters of the query in one sequence, while another node may have used a different sequence. Additionally, the distributed query explain plan can provide execution tracing, rendering information about the execution time of each step, total execution time and the like.
    • 描述了与分布式数据系统一起使用的查询解释计划,以帮助开发人员和IT专家检测出瓶颈,并确定哪些查询对于运行缓慢的系统而言是错误的。 根据实施例,分布式数据网格利用设施提供分布式解释计划。 此分布式解释计划提供了群集中每个节点如何回答查询的可见性。 例如,一个节点可以以一个序列应用查询的过滤器,而另一个节点可能已经使用了不同的序列。 此外,分布式查询说明计划可以提供执行跟踪,呈现关于每个步骤的执行时间,总执行时间等的信息。
    • 4. 发明授权
    • Code generation in the presence of paged memory
    • 存在分页内存的代码生成
    • US08341609B2
    • 2012-12-25
    • US11698638
    • 2007-01-26
    • Robert H. LeeDavid UnietisMark Jungerman
    • Robert H. LeeDavid UnietisMark Jungerman
    • G06F9/44G06F9/45G06F9/26
    • G06F8/4434G06F9/45504
    • A computer is programmed to automatically identify multiple sequences of executable code such that each sequence fits within a page of memory. When the executable code comprising several sequences is loaded into the paged memory, each sequence is placed in its own page. The computer is further programmed to prepare a number of structures which identify a corresponding number of instructions that transfer control between sequences. Each structure identifies at least a control transfer instruction in one sequence and a target in another sequence. When loading the sequences into memory, the structures are used to replace destination addresses of control transfers between sequences with new addresses derived from base addresses of pages that have been allocated in memory to hold the sequences.
    • 计算机被编程为自动识别可执行代码的多个序列,使得每个序列适合存储器的页面。 当包含多个序列的可执行代码被加载到分页存储器中时,每个序列被放置在其自己的页面中。 计算机还被编程为准备多个结构,其识别在序列之间传送控制的相应数量的指令。 每个结构至少标识一个序列中的控制传输指令和另一个序列中的目标。 当将序列加载到存储器中时,结构用于替换序列之间的控制传输的目的地地址,其中新地址是从在存储器中分配的用于保存序列的页的基址导出的。
    • 6. 发明授权
    • Low voltage transient current limiting circuit
    • 低电压瞬态电流限制电路
    • US4924342A
    • 1990-05-08
    • US228829
    • 1988-08-03
    • Robert H. Lee
    • Robert H. Lee
    • H02H9/00H02H9/02
    • H02H9/001H02H9/02Y10S174/17
    • A polyphase AC current limiting circuit, which incorporates improvements in control methods and circuitry that operate to avoid high rates of current change which occur upon initiation of a branch load fault and when the branch load fault is suddenly cleared. This "soft" start and "soft" load-off characteristic, reduces the voltage transients imposed on the AC power source and bus to relative insignificance compared with the voltage transients imposed by prior art current limiting circuits. The invention AC current limiting circuit comprises a high impedance circuit connected in parallel with a low impedance circuit, a load-off circuit connected in shunt with the device output power lines, and a control means for controlling the switching devices. When a branch load fault is sensed, the control means turns off the switches in the low impedance circuit through which normal current flows, and turns on the switches in the high impedance circuit, starting phased back, so that the initial current step is typically 100 percent of rated load current. Within a few cycles, the switches are phased to full on and the maximum current is limited by an inductor in series with the switches in the high impedance circuit. When the load fault is suddenly cleared and current drops to zero, the load-off circuit is energized and current continues to flow at graduated lower levels until the circuit is switched off. In the event that the load fault does not clear, the switches in the high impedance circuit are turned off, stopping current flow and a trip signal is transmitted to trip open an external input circuit breaker.
    • 多相交流限流电路,其结合了控制方法和电路的改进,其操作以避免在分支负载故障开始时和分支负载故障突然清除时发生的高电流变化率。 这种“软”启动和“软”负载特性,与现有技术的限流电路施加的电压瞬变相比,将交流电源和总线上的电压瞬变减小到相对无关紧要。 本发明的交流限流电路包括与低阻抗电路并联连接的高阻抗电路,与设备输出电源线分流连接的负载断开电路以及用于控制开关器件的控制装置。 当检测到分支负载故障时,控制装置关闭正常电流流动的低阻抗电路中的开关,并将高阻抗电路中的开关导通,并将其分阶段开始,使得初始电流步长通常为100 额定负载电流百分比。 在几个周期内,开关被定相完全接通,并且最大电流受到与高阻抗电路中的开关串联的电感器的限制。 当负载故障突然清除并且电流下降到零时,负载断开电路通电,电流继续以等级降低的电平流动,直到电路关闭。 在负载故障不清除的情况下,高阻抗电路中的开关断开,停止电流流动,并发送跳闸信号以跳闸打开外部输入断路器。
    • 8. 再颁专利
    • Step switched PWM sine generator
    • 步进开关PWM正弦发生器
    • USRE41040E1
    • 2009-12-15
    • US11115103
    • 2005-04-25
    • Yuri KhersonskyRobert H. Lee
    • Yuri KhersonskyRobert H. Lee
    • H02M1/12
    • H02M7/49
    • Apparatus for generating a high time-varying AC voltage using low voltage power semiconductors arranged in series bridge circuits, each powered by an independent DC source. At least one bipolar output pulse width modulation bridge circuit and at least a pair of bipolar output square wave generator bridge circuits have their outputs added together and passed through a low pass filter to form a time-varying, typically sinusoidal, AC output waveform. A first square wave generator has an output with a relative magnitude of 6, a second square wave generator has an output with a relative magnitude of 2 and the pulse width modulator has an output with a relative magnitude of 1. Additional square wave generators of relative magnitude 6 may be added to increase the output voltage.
    • 用于使用布置在串联桥电路中的低电压功率半导体产生高时变AC电压的装置,每个由独立DC源供电。 至少一个双极性输出脉宽调制电桥电路和至少一对双极性输出方波发生器电路电路将它们的输出相加在一起,并通过低通滤波器以形成时变的,通常是正弦的交流输出波形。 第一方波发生器具有相对值为6的输出,第二方波发生器具有相对幅度为2的输出,并且脉冲宽度调制器具有相对值为1的输出。相对值的附加方波发生器 可增加幅度6以增加输出电压。
    • 10. 发明授权
    • Constant speed and frequency generating system
    • 恒速和频率发生系统
    • US4806841A
    • 1989-02-21
    • US162025
    • 1988-02-29
    • Robert H. LeeAlexander Levran
    • Robert H. LeeAlexander Levran
    • H02P9/42H02P9/30H02K7/10
    • H02P9/42
    • An output frequency control circuit is mounted on the rotating shaft connecting a motor and generator. The motor-generator system includes exciter circuits, an input power factor control and an output voltage regulator. The input power factor control ensures that the motor input power factor is unity, which is desirable for motor control. The frequency control circuit responds to variations in the AC power source frequency by generating low frequency excitation to boost or buck the operational speed of the machine, causing the generator output frequency to remain constant at a selected frequency output irrespective of input power source frequency variation. The output frequency may be selected over a given range from a control panel adjustment pot.The major innovation is that the entire frequency control circuit is shaft-mounted and requires no slip-rings or magnetic transformers for signal transfer, thus reducing the possibilities of mechanical failure. A second innovation is that the motor input power factor is held at unity. A third innovation is that the system is enabled to ride through `brownouts` or short term input power failure.
    • 输出频率控制电路安装在连接电动机和发电机的旋转轴上。 电动发电机系统包括励磁电路,输入功率因数控制和输出电压调节器。 输入功率因数控制确保电机输入功率因数为1,这对于电机控制是理想的。 频率控制电路通过产生低频激励来响应交流电源频率的变化,以升高或降低机器的操作速度,使得发生器输出频率在选定的频率输出处保持恒定,而与输入电源频率变化无关。 输出频率可以在一个给定的范围内从一个控制面板调节锅中选择。 主要的创新是整个频率控制电路是轴安装的,不需要滑环或磁变压器进行信号传输,从而减少机械故障的可能性。 第二个创新是电机输入功率因数保持一致。 第三个创新是系统能够通过“掉电”或短期输入电源故障。