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1. 发明授权

US07859292B1 Methods and circuitry for reconfigurable SEU/SET tolerance 有权
标题翻译：用于可重新配置的SEU / SET公差的方法和电路
公开(公告)号：US07859292B1
公开(公告)日：2010-12-28
申请号：US12502575
申请日：2009-07-14
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： H03K19/003 , H03K19/007
CPC分类号： H03K19/0033 , H03K19/0075 , H03K19/17736 , H03K19/17748 , H03K19/17764 , H03K19/23 , Y10T29/49002
摘要： A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.
摘要翻译：在一个实施例中公开了一种装置，其具有多个相同的可编程功能元件组，可编程布线资源以及校正错误的多数选民。选民接受冗余模式和分割模式的模式输入。在冗余模式下，可编程功能元件是相同的，并且被相同地编程，所以选票器产生对应于大部分同意的输入的输出。在分割模式中，每个选民选择特定的可编程功能元素输出作为投票者的输出。因此，在分割模式中，可编程功能元件可以执行不同的功能，独立操作和/或连接在一起以处理相同问题的不同部分。

2. 发明授权

US06943621B1 Auto-routable, configurable, daisy chainable data acquisition system 失效
标题翻译：自动路由，可配置，可菊花链式数据采集系统
公开(公告)号：US06943621B1
公开(公告)日：2005-09-13
申请号：US10443234
申请日：2003-05-21
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： H03F1/14
CPC分类号： H03F1/0277 , H03F2200/261 , H03F2203/45138
摘要： A method and apparatus for an acquisition system includes a plurality of sensor input signal lines. At least one of the plurality of sensor input signal lines operatively connects to at least one of a plurality of amplifier circuits. At least one of the plurality of amplifier circuits operatively connects to at least one of a plurality of filter circuits.
摘要翻译：用于采集系统的方法和装置包括多个传感器输入信号线。多个传感器输入信号线中的至少一个可操作地连接到多个放大器电路中的至少一个。多个放大器电路中的至少一个可操作地连接到多个滤波器电路中的至少一个。

3. 发明申请

US20110012638A1 METHODS AND CIRCUITRY FOR RECONFIGURABLE SEU/SET TOLERANCE 有权
标题翻译：可重新配置SEU /容差的方法和电路
公开(公告)号：US20110012638A1
公开(公告)日：2011-01-20
申请号：US12502575
申请日：2009-07-14
申请人： Robert L. Shuler, JR.
发明人： Robert L. Shuler, JR.
IPC分类号： H03K19/003 , H01S4/00
CPC分类号： H03K19/0033 , H03K19/0075 , H03K19/17736 , H03K19/17748 , H03K19/17764 , H03K19/23 , Y10T29/49002
摘要： A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.
摘要翻译：在一个实施例中公开了一种装置，其具有多个相同的可编程功能元件组，可编程布线资源以及校正错误的多数选民。选民接受冗余模式和分割模式的模式输入。在冗余模式下，可编程功能元件是相同的，并且被相同地编程，所以选票器产生对应于大部分同意的输入的输出。在分割模式中，每个选民选择特定的可编程功能元素输出作为投票者的输出。因此，在分割模式中，可编程功能元件可以执行不同的功能，独立操作和/或连接在一起以处理相同问题的不同部分。

4. 发明授权

US06943619B1 Practical active capacitor filter 失效
标题翻译：实用有源电容滤波器
公开(公告)号：US06943619B1
公开(公告)日：2005-09-13
申请号：US10443233
申请日：2003-05-21
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： H03K5/00
CPC分类号： H03H11/483 , H03H11/1234 , H03H11/1278
摘要： A method and apparatus is described that filters an electrical signal. The filtering uses a capacitor multiplier circuit where the capacitor multiplier circuit uses at least one amplifier circuit and at least one capacitor. A filtered electrical signal results from a direct connection from an output of the at least one amplifier circuit.
摘要翻译：描述了对电信号进行滤波的方法和装置。滤波使用电容器乘法器电路，其中电容器乘法器电路使用至少一个放大器电路和至少一个电容器。滤波后的电信号来自至少一个放大器电路的输出的直接连接。

5. 发明授权

US06377097B1 Method and apparatus for reducing the vulnerability of latches to single event upsets 失效
标题翻译：用于减少锁存器对单个事件扰乱的脆弱性的方法和装置
公开(公告)号：US06377097B1
公开(公告)日：2002-04-23
申请号：US09525371
申请日：2000-03-13
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： H03K3356
CPC分类号： H03K3/356165 , H03K3/0375
摘要： A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.
摘要翻译：延迟电路包括具有输入和输出节点的第一网络，具有输入和输出的第二网络，第二网络的输入耦合到第一网络的输出节点。第一网络和第二网络被配置为使得在第一网络的输入处的毛刺具有标准毛刺时间或更短的大约二分之一的长度不会导致第二网络的输出处的电压交叉阈值，在第一网络的输入处的毛刺具有大约二分之二和两个标准毛刺时间之间的长度，导致第二网络的输出处的电压跨越阈值小于毛刺的长度，以及在具有大于大约两个标准毛刺时间的长度的第一网络的输入处的毛刺导致第二网络的输出处的电压大约在毛刺时间内跨越阈值。该方法可以减少锁存器对单个事件的影响。锁存器包括具有输入和输出的门，以及从输出到门的输入的反馈路径。该方法包括将延迟插入反馈路径并在门中提供延迟。

6. 发明授权

US06492857B2 Method and apparatus for reducing the vulnerability of latches to single event upsets 失效
标题翻译：用于减少锁存器对单个事件扰乱的脆弱性的方法和装置
公开(公告)号：US06492857B2
公开(公告)日：2002-12-10
申请号：US09840684
申请日：2001-04-20
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： H03K3037
CPC分类号： H03K3/356165 , H03K3/0375
摘要： A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.
摘要翻译：延迟电路包括具有输入和输出节点的第一网络，具有输入和输出的第二网络，第二网络的输入耦合到第一网络的输出节点。第一网络和第二网络被配置为使得在第一网络的输入处的毛刺具有标准毛刺时间或更短的大约二分之一的长度不会导致第二网络的输出处的电压交叉阈值，在第一网络的输入处的毛刺具有大约二分之二和两个标准毛刺时间之间的长度，导致第二网络的输出处的电压跨越阈值小于毛刺的长度，以及在具有大于大约两个标准毛刺时间的长度的第一网络的输入处的毛刺导致第二网络的输出处的电压在大概时间内穿过阈值。一种方法降低了锁存器的脆弱性单个事件的烦恼。锁存器包括具有输入和输出的门，以及从输出到门的输入的反馈路径。该方法包括将延迟插入反馈路径并在门中提供延迟。

7. 发明授权

US4912629A Real-time garbage collection for list processing using restructured cells for increased reference counter size 失效
标题翻译：使用重组单元进行列表处理的实时垃圾收集，以增加参考计数器大小
公开(公告)号：US4912629A
公开(公告)日：1990-03-27
申请号：US878916
申请日：1986-06-26
申请人： Robert L. Shuler, Jr.
发明人： Robert L. Shuler, Jr.
IPC分类号： G06F12/02
CPC分类号： G06F12/0261 , Y10S707/99957
摘要： In a list processing system, small reference counters are maintained in conjunction with memory cells for the purpose of identifying memory cells that become available for re-use. The counters are updated as references to the cells are created and destroyed, and when a counter of a cell is decremented to logical zero the cell is immediately returned to a list of free cells. In those cases where a counter must be incremented beyond the maximum value that can be represented in a small counter, the cell is restructured so that the additional reference count can be represented. The restructuring involves allocating an additional cell, distributing counter, tag, and pointer information among the two cells, and linking both cells appropriately into the existing list structure.
摘要翻译：在列表处理系统中，小型参考计数器与存储器单元一起被保持，以便识别可用于重复使用的存储器单元。更新计数器，因为对单元格的引用被创建和销毁，并且当单元的计数器递减到逻辑零时，单元格立即返回到空闲单元列表。在计数器必须增加超过可以在小计数器中表示的最大值的情况下，重新组合单元，以便可以表示额外的引用计数。重组涉及在两个小区之间分配附加小区，分配计数器，标签和指针信息，并且将两个小区适当地链接到现有的列表结构中。

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