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1. 发明申请

US20080265379A1 Laser Diode Orientation on Mis-Cut Substrates 有权
标题翻译：错误切割基板上的激光二极管方向
公开(公告)号：US20080265379A1
公开(公告)日：2008-10-30
申请号：US11994406
申请日：2006-06-27
申请人： George R. Brandes , Robert P. Vaudo , Xueping Xu
发明人： George R. Brandes , Robert P. Vaudo , Xueping Xu
IPC分类号： H01L29/04
CPC分类号： H01S5/32341 , Y10S438/973
摘要： A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the direction predominantly towards either the or the family of directions. For a off-cut substrate, a laser diode cavity (207) may be oriented along the direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For off-cut substrate, the laser diode cavity may be oriented along the direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.
摘要翻译：一种微电子组件，其中半导体器件结构定向地定位在离轴衬底（201）上。在说明性实施例中，激光二极管定向在GaN衬底（201）上，其中GaN衬底包括从主要朝向<1120>或<11 00>的方向从<0001>方向偏离的GaN（0001）家庭方向。对于<11 20>截割基板，激光二极管空腔（207）可以沿着平行于基板（201）的格子表面台阶（202）的<100°方向取向，以便具有切割的激光刻面这与表面晶格步骤正交。对于<11 00>切割衬底，激光二极管腔可以沿着与衬底（201）的晶格表面台阶（207）正交的<100°方向取向，以便提供与表面晶格步骤。

2. 发明申请

US20080124510A1 LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GAN SUBSTRATE AND PROCESS FOR MAKING THE SAME 有权
标题翻译：大面积，均匀的低偏差密度基体及其制造方法
公开(公告)号：US20080124510A1
公开(公告)日：2008-05-29
申请号：US12026552
申请日：2008-02-05
申请人： Xueping Xu , Robert P. Vaudo
发明人： Xueping Xu , Robert P. Vaudo
IPC分类号： C01B21/06 , B32B3/02
CPC分类号： C30B29/406 , C30B25/02 , C30B29/403 , H01L21/0237 , H01L21/0254 , H01L31/184 , H01L33/0075 , Y10T428/21 , Y10T428/265
摘要： Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
摘要翻译：面积为至少2cm 2的大面积单晶III-V族氮化物材料，具有均匀低位错密度，不超过3×10 6个位错/ cm 2 并且包括具有升高的杂质浓度的多个不同区域，其中每个不同区域具有大于50微米的至少一个尺寸。这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一相，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少10 2个/厘米2，和（ii）生长的第二阶段在填埋条件下的III-V族氮化物材料。

3. 发明授权

US06943095B2 Low defect density (Ga, A1, In) N and HVPE process for making same 失效
标题翻译：低缺陷密度（Ga，A1，In）N和HVPE制程相同
公开(公告)号：US06943095B2
公开(公告)日：2005-09-13
申请号：US10103226
申请日：2002-03-21
申请人： Robert P. Vaudo , Vivek M. Phanse , Michael A. Tischler
发明人： Robert P. Vaudo , Vivek M. Phanse , Michael A. Tischler
IPC分类号： C30B33/00 , H01L21/205 , H01L33/00 , H01L21/20
CPC分类号： C30B33/00 , B82Y15/00 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0242 , H01L21/0254 , H01L21/0262 , H01L33/007 , H01L33/0075 , H01L33/0079
摘要： A low defect density (Ga,Al,In)N material. The (Ga, Al, In)N material may be of large area, crack-free character, having a defect density as low as 3×106 defects/cm2 or lower. Such (Ga,Al,In)N material is useful as a substrate for epitaxial growth of Group III-V nitride device structures thereon.
摘要翻译：低缺陷密度（Ga，Al，In）N材料。（Ga，Al，In）N材料可能面积大，无裂纹，具有低至3×10 6缺陷/ cm 2以下的缺陷密度。这种（Ga，Al，In）N材料可用作其上的III-V族氮化物器件结构的外延生长的衬底。

4. 发明授权

US06765240B2 Bulk single crystal gallium nitride and method of making same 失效
标题翻译：散装单晶氮化镓及其制造方法
公开(公告)号：US06765240B2
公开(公告)日：2004-07-20
申请号：US09933943
申请日：2001-08-21
申请人： Michael A. Tischler , Thomas F. Kuech , Robert P. Vaudo
发明人： Michael A. Tischler , Thomas F. Kuech , Robert P. Vaudo
IPC分类号： H01L310328
CPC分类号： C30B33/00 , B82Y15/00 , C30B23/02 , C30B25/02 , C30B25/18 , C30B29/36 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/02381 , H01L21/0242 , H01L21/02439 , H01L21/0245 , H01L21/02458 , H01L21/02507 , H01L21/02529 , H01L21/0254 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/02581 , H01L21/0262 , H01L21/02664 , H01L33/007 , H01L33/0075 , H01L33/0079 , Y10S117/915 , Y10T428/13 , Y10T428/21
摘要： A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.
摘要翻译：一种单晶M * N制品，其可以通过包括以下步骤的方法制备：提供具有与M * N外延相容的结晶表面的材料的基材; 在衬底的表面上沉积单晶M * N层; 从单晶M * N层除去衬底，例如用施加到衬底去除其的蚀刻剂，得到单晶M * N层作为单晶M * N制品。本体单晶M * N制品适用于在其上制造微电子结构的基底，以产生包含本体单晶M * N基底或其前体结构的微电子器件。

5. 发明授权

US06447604B1 METHOD FOR ACHIEVING IMPROVED EPITAXY QUALITY (SURFACE TEXTURE AND DEFECT DENSITY) ON FREE-STANDING (ALUMINUM, INDIUM, GALLIUM) NITRIDE ((AL,IN,GA)N) SUBSTRATES FOR OPTO-ELECTRONIC AND ELECTRONIC DEVICES 有权
标题翻译：用于光电子和电子器件的用于实现改进的外延质量（表面纹理和缺陷密度）的方法在自由放置（铝，铟，镓）氮化物（（AL，IN，GA）N）衬底
公开(公告)号：US06447604B1
公开(公告)日：2002-09-10
申请号：US09605195
申请日：2000-06-28
申请人： Jeffrey S. Flynn , George R. Brandes , Robert P. Vaudo , David M. Keogh , Xueping Xu , Barbara E. Landini
发明人： Jeffrey S. Flynn , George R. Brandes , Robert P. Vaudo , David M. Keogh , Xueping Xu , Barbara E. Landini
IPC分类号： C30B2514
CPC分类号： C30B25/02 , C30B23/002 , C30B23/02 , C30B25/00 , C30B25/183 , C30B29/403 , C30B29/406 , H01L21/02389 , H01L21/0243 , H01L21/02433 , H01L21/0254 , H01L21/0262 , H01L21/02634 , H01L21/02636 , H01L21/02658 , H01L33/32 , H01S5/1228 , H01S5/1231 , H01S5/2095 , H01S5/32341
摘要： A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.
摘要翻译： III-V族氮化物同质外延微电子器件结构，其包括III-V族氮化物材料衬底上的III-V族同质外延层，例如独立性。描述了各种处理技术，包括通过使用III族源材料和氮源材料通过VPE工艺沉积III-V族氮化物同质外延层，在相应的III-V族氮化物材料基板上形成III-V族氮化物同质外延层的方法在包括约1至约105范围内的V / III比的工艺条件下，氮源材料分压在约1至约103托的范围内，生长温度在约500至约1250摄氏度的范围内，并且生长速率在约0.1至约500微米/小时的范围内。 III-V族氮化物同质外延微电子器件结构有用地用于诸如UV LED，高电子迁移率晶体管等的器件应用中。

6. 发明授权

US08390101B2 High voltage switching devices and process for forming same 有权
标题翻译：高压开关器件及其形成工艺
公开(公告)号：US08390101B2
公开(公告)日：2013-03-05
申请号：US13428039
申请日：2012-03-23
申请人： Jeffrey S. Flynn , George R. Brandes , Robert P. Vaudo
发明人： Jeffrey S. Flynn , George R. Brandes , Robert P. Vaudo
IPC分类号： H01L29/20
CPC分类号： H01L29/2003 , C30B25/02 , C30B29/40 , C30B29/406 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02576 , H01L21/02664 , H01L29/861 , H01L29/868 , H01L29/872
摘要： The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration ( 2 KV).
摘要翻译：本发明涉及包括肖特基二极管，PN二极管和PIN二极管的各种开关器件结构，其特征在于低缺陷密度，低裂纹密度，低凹坑密度和足够厚度（>2.5μm）低掺杂剂浓度的GaN层（在导电GaN层上生长的<1E16cm-3）。这些器件在异质外延衬底（<2KV）上实现了更高的击穿电压，并且在同质外延衬底（> 2KV）上实现了极高的击穿电压。

7. 发明授权

US08378463B2 Orientation of electronic devices on mis-cut substrates 有权
标题翻译：电子设备在误切基板上的方向
公开(公告)号：US08378463B2
公开(公告)日：2013-02-19
申请号：US12974332
申请日：2010-12-21
申请人： George R. Brandes , Robert P. Vaudo , Xueping Xu
发明人： George R. Brandes , Robert P. Vaudo , Xueping Xu
IPC分类号： H01L29/04
CPC分类号： H01S5/32341 , Y10S438/973
摘要： A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the direction predominantly towards either the or the family of directions. For a off-cut substrate, a laser diode cavity may be oriented along the direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a off-cut substrate, the laser diode cavity may be oriented along the direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.
摘要翻译：一种微电子组件，其中半导体器件结构定向地定位在离轴衬底上。在说明性实施方案中，激光二极管定向在GaN衬底上，其中GaN衬底包括从（0001）方向偏离的GaN（0001）表面，主要朝向<11 20>或<1100> 方向。对于<11 20>截割衬底，激光二极管空腔可以沿着平行于衬底的晶格表面台阶的<100°方向取向，以便具有与表面晶格步骤正交的切割的激光刻面。对于<100>切割衬底，激光二极管空腔可以沿着与衬底的晶格表面台阶正交的<100°方向取向，以便提供与表面晶格步骤对准的切割的激光刻面。

8. 发明申请

US20110140122A1 LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GaN SUBSTRATE AND PROCESS FOR MAKING THE SAME 有权
标题翻译：大面积的均匀低折射密度GaN衬底及其制造方法
公开(公告)号：US20110140122A1
公开(公告)日：2011-06-16
申请号：US13008008
申请日：2011-01-17
申请人： XUEPING XU , ROBERT P. VAUDO
发明人： XUEPING XU , ROBERT P. VAUDO
IPC分类号： H01L29/38 , H01L29/20 , H01L21/205
CPC分类号： C30B29/406 , C30B25/02 , C30B29/403 , H01L21/0237 , H01L21/0254 , H01L31/184 , H01L33/0075 , Y10T428/21 , Y10T428/265
摘要： Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
摘要翻译：具有至少2cm 2面积的大面积单晶III-V族氮化物材料，具有均匀低位错密度，每平方厘米生长表面积不超过3×106位错，并且包括具有升高的杂质浓度的多个不同区域，其中每个不同的区域具有大于50微米的至少一个尺寸。这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一相，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少102个凹坑/ cm 2，和（ii）在凹坑填充条件下生长III-V族氮化物材料的第二阶段。

9. 发明授权

US07323256B2 Large area, uniformly low dislocation density GaN substrate and process for making the same 有权
标题翻译：大面积均匀低位错密度GaN衬底及其制造方法
公开(公告)号：US07323256B2
公开(公告)日：2008-01-29
申请号：US10712351
申请日：2003-11-13
申请人： Xueping Xu , Robert P. Vaudo
发明人： Xueping Xu , Robert P. Vaudo
IPC分类号： B32B9/00
CPC分类号： C30B29/406 , C30B25/02 , C30B29/403 , H01L21/0237 , H01L21/0254 , H01L31/184 , H01L33/0075 , Y10T428/21 , Y10T428/265
摘要： Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm−2, and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
摘要翻译：大面积均匀低位错密度的单晶III-V族氮化物材料，例如，具有大于15cm 2的大面积的氮化镓，至少1mm的厚度，不是的平均位错密度超过5E5cm -2，位错密度标准偏差比小于25％。这样的材料可以通过以下工艺在基底上形成，该方法包括：（i）在凹陷生长条件下在衬底上生长III-V族氮化物材料的第一相，例如在III的生长表面的至少50％上形成凹坑 -V氮化物材料，其中生长表面上的凹坑密度为生长表面的至少10 2个/厘米2，和（ii）生长的第二阶段在填埋条件下的III-V族氮化物材料。

10. 发明授权

US6156581A GaN-based devices using (Ga, AL, In)N base layers 失效
标题翻译：使用（Ga，AL，In）N基层的GaN基器件
公开(公告)号：US6156581A
公开(公告)日：2000-12-05
申请号：US984473
申请日：1997-12-03
申请人： Robert P. Vaudo , Joan M. Redwing , Michael A. Tischler , Duncan W. Brown
发明人： Robert P. Vaudo , Joan M. Redwing , Michael A. Tischler , Duncan W. Brown
IPC分类号： C30B33/00 , H01L21/205 , H01L33/00
CPC分类号： C30B33/00 , B82Y15/00 , C30B23/02 , C30B25/02 , C30B25/18 , C30B29/36 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/02381 , H01L21/0242 , H01L21/02439 , H01L21/0245 , H01L21/02458 , H01L21/02507 , H01L21/02529 , H01L21/0254 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/02581 , H01L21/0262 , H01L21/02664 , H01L33/007 , H01L33/0075 , H01L33/0079 , Y10S117/915 , Y10T428/13 , Y10T428/21
摘要： A method of forming a (gallium, aluminum, indium) nitride base layer on a substrate for subsequent fabrication, e.g., by MOCVD or MBE, of a microelectronic device structure thereon. Vapor-phase (Ga, Al, In) chloride is reacted with a vapor-phase nitrogenous compound in the presence of the substrate, to form (Ga, Al, In) nitride. The (Ga, Al, In) nitride base layer is grown on the substrate by HVPE, to yield a microelectronic device base comprising a substrate with the (Ga, Al, In) nitride base layer thereon. The product of such HVPE process comprises a device quality, single crystal crack-free base layer of (Ga, Al, In) N on the substrate, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cm.sup.-2 or lower. Microelectronic devices thereby may be formed on the base layer, over a substrate of a foreign (poor lattice match) material, such as sapphire. Devices which may be fabricated utilizing the HVPE base layer of the invention include light emitting diodes, detectors, transistors, and semiconductor lasers.
摘要翻译：在衬底上形成（镓，铝，铟）氮化物基底层的方法，用于例如通过MOCVD或MBE制造其上的微电子器件结构。在衬底存在下，使气相（Ga，Al，In）与气相含氮化合物反应，形成（Ga，Al，In）氮化物。（Ga，Al，In）氮化物基层通过HVPE在衬底上生长，得到包含其上具有（Ga，Al，In）氮化物基底层的衬底的微电子器件基底。这种HVPE工艺的产物包括在衬底上的（Ga，Al，In）N的器件质量，单晶无裂纹基底层，其中基底层的厚度可以例如为2 微米和更大，并且基底层的缺陷密度可以例如为1E8cm-2或更低的数量级。因此，微电子器件可以形成在基底层上，在诸如蓝宝石的外来（差的晶格匹配）材料的衬底上。可以使用本发明的HVPE基层制造的器件包括发光二极管，检测器，晶体管和半导体激光器。

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