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1. 发明授权

US08756541B2 Relative ordering circuit synthesis 有权
标题翻译：相对排序电路综合
公开(公告)号：US08756541B2
公开(公告)日：2014-06-17
申请号：US13431368
申请日：2012-03-27
申请人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
发明人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.
摘要翻译：本文提供了相对排序电路合成的系统和方法。一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。本文还描述了其它实施例和方面。

2. 发明授权

US08365114B2 Logic modification synthesis 有权
标题翻译：逻辑修改综合
公开(公告)号：US08365114B2
公开(公告)日：2013-01-29
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.
摘要翻译：正在识别两个电路，一个原始和一个修改的电路，原始电路具有第一逻辑，并且该修改的电路具有第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化。在原始电路中检测到等效线，使得第一和第二逻辑等效于从电路输入到等价线。至少一个变化点位于与等价线相邻的逻辑门之间。如果可观察性条件得到满足，则可以接受更改点。可观察性条件在布尔满足度（SAT）公式中进行检查。通过使用SAT和布尔方程求解技术，使得第一逻辑变为等同于第二逻辑的方式，导出用于验证的变化点的替代逻辑。

3. 发明申请

US20120054699A1 CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE MICROPROCESSOR DESIGNS 有权
标题翻译：用于高性能微处理器设计的大块和结构化合成
公开(公告)号：US20120054699A1
公开(公告)日：2012-03-01
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

4. 发明授权

US08122400B2 Logic difference synthesis 有权
标题翻译：逻辑差分合成
公开(公告)号：US08122400B2
公开(公告)日：2012-02-21
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

5. 发明申请

US20110004857A1 LOGIC DIFFERENCE SYNTHESIS 有权
标题翻译：逻辑差异综合
公开(公告)号：US20110004857A1
公开(公告)日：2011-01-06
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

6. 发明申请

US20090070719A1 Logic Block Timing Estimation Using Conesize 有权
标题翻译：使用锥形的逻辑块时序估计
公开(公告)号：US20090070719A1
公开(公告)日：2009-03-12
申请号：US11853235
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
摘要翻译：用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。存储器可以提供逻辑块的延迟对锥形值。该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

7. 发明申请

US20080281572A1 INTEGRATED CIRCUIT (IC) DESIGN METHOD AND METHOD OF ANALYZING RADIATION-INDUCED SINGLE-EVENT UPSETS IN CMOS LOGIC DESIGNS 审中-公开
标题翻译：集成电路（IC）设计方法和分析CMOS逻辑设计中辐射诱导的单事件的方法
公开(公告)号：US20080281572A1
公开(公告)日：2008-11-13
申请号：US11746709
申请日：2007-05-10
申请人： Ruchir Puri , Henry H. K. Tang , Kim Yaw Tong
发明人： Ruchir Puri , Henry H. K. Tang , Kim Yaw Tong
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/16
摘要： A logic design tool, a tool for analyzing soft error sensitivities in logic, and a program product for logic design. A particle generator simulates events likely to occur for a given operating environment. A pre-characterizer provides circuit block responses to simulated events. A circuit response simulator simulates events in a logic design and provides an indication of soft error sensitivity for the design. Based on the soft error sensitivity indication, the design may be modified to reduce the overall soft error sensitivity.
摘要翻译：逻辑设计工具，用于分析逻辑中的软错误灵敏度的工具，以及用于逻辑设计的程序产品。粒子发生器模拟给定操作环境可能发生的事件。预特征化器为模拟事件提供电路块响应。电路响应仿真器模拟逻辑设计中的事件，并为设计提供软错误灵敏度的指示。基于软错误灵敏度指示，可以修改设计以降低整体软错误灵敏度。

8. 发明申请

US20080165521A1 THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS 审中-公开
标题翻译：用于自检和自修复集成电路的三维架构
公开(公告)号：US20080165521A1
公开(公告)日：2008-07-10
申请号：US11621188
申请日：2007-01-09
申请人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
发明人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
IPC分类号： H05K7/00 , H01L21/50
CPC分类号： H01L24/83 , H01L21/6835 , H01L21/8221 , H01L24/26 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L2221/68354 , H01L2224/8385 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/07802 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.
摘要翻译：三维结构芯片包括基本芯片，其包括集成在其上并被配置为执行电信号操作的单元。从基层分开制造有源层。有源层包括用于服务于基片的单元的部件。有源层被结合到基片，使得该元件在该单元的垂直方向上对准。电连接通过基底芯片和有源层中的至少一个的垂直层将单元连接到部件。

9. 发明申请

US20070234259A1 Cell placement in circuit design 审中-公开
标题翻译：电路设计中的电池放置
公开(公告)号：US20070234259A1
公开(公告)日：2007-10-04
申请号：US11397586
申请日：2006-04-04
申请人： Anthony Drumm , Pooja Kotecha , Ruchir Puri , Louise Trevillyan
发明人： Anthony Drumm , Pooja Kotecha , Ruchir Puri , Louise Trevillyan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072
摘要： A solution for managing a circuit design, which enables a cell to be incrementally placed in the circuit design based on a resulting wiring distance is provided. A cell to be placed in the circuit design is obtained along with a corresponding set of nets in the circuit design to which the cell is to be connected. A routing grid, which defines a plurality of tiles in the circuit design for consideration in placing the cell, can be generated based on the set of nets for the cell. A wire distance measure can be calculated for each of the tiles in the routing grid using the set of nets. The wire distance measure is then used to identify a target tile for placing the cell. The target tile can be used to find an exact and/or rough placement for the cell.
摘要翻译：提供了一种用于管理电路设计的解决方案，其使得能够基于所得到的布线距离将单元递增地放置在电路设计中。获得放置在电路设计中的单元以及连接单元的电路设计中的相应的一组网络。可以基于小区的网络集合来生成在电路设计中定义多个瓦片以便放置单元的布线网格。可以使用网络集合为路由网格中的每个瓦片计算线距测量。然后使用线距测量来识别用于放置单元的目标瓦片。目标瓦片可用于为单元格找到精确和/或粗略的布局。

10. 发明申请

US20060279334A1 SINGLE SUPPLY LEVEL CONVERTER 有权
标题翻译：单电源电平转换器
公开(公告)号：US20060279334A1
公开(公告)日：2006-12-14
申请号：US11466754
申请日：2006-08-23
申请人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译：用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

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