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1. 发明授权

US10462757B2 Automatic gain control based on signal spectrum sensing 有权
公开(公告)号：US10462757B2
公开(公告)日：2019-10-29
申请号：US15259017
申请日：2016-09-07
申请人： Signalchip Innovations Private Limited
发明人： Aravind Ganesan , Himamshu Gopalakrishna Khasnis
IPC分类号： H04W52/52 , H04L27/26 , H04B17/373 , H04B17/391
摘要： Disclosed herein is a method for automatic gain control based on signal spectrum sensing. Spectral sensing techniques may be employed to detect the presence or absence of interference and also determine a frequency location of the interference and power level estimates of a desired signal. The method includes running an algorithm to measure the energy periodically to track the changes as blockers that were not prominent while experiencing deep fade and those that will affect performance when it is out of the deep fade. The method enables predicting a level of degradation for various front-end settings and enables selection of an optimum setting. In an embodiment, the spectral sensing may be performed either in analog domain using narrowband tunable filters. In an embodiment, the spectral sensing may be performed digitally using Fast fourier transform (FFT), Goertzel algorithm, or power detection techniques.

2. 发明申请

US20180321941A1 SYSTEM AND METHOD FOR REDUCING NON-LINEARITY IN MIXED SIGNAL PROCESSING USING COMPLEX POLYNOMIAL VECTOR PROCESSOR 审中-公开
公开(公告)号：US20180321941A1
公开(公告)日：2018-11-08
申请号：US15969356
申请日：2018-05-02
申请人： Signalchip Innovations Private Limited
发明人： Himamshu Gopalakrishna Khasnis , Sukrutha Bharadwaj Hebbagilu Krishna
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F9/30036 , G06F7/544 , G06F9/3001 , G06F9/30134 , G06F15/8053 , G06F15/8076
摘要： A system for reducing non-linearity in mixed signal processing using complex polynomial vector processor 102 is provided. The complex polynomial vector processor 102 includes a data processing unit (104) and a co-efficient feeder unit (106). The data processing unit (104) converts a high-speed data stream into a polar-like format (PL) data and calculates required polynomial powers for the high-speed data stream using the PL format data. The data processing unit (104) includes a multiplier accumulator (MAC) unit (206) that generates processed high-speed data and a delay unit (208) that combines time separated input with the processed high-speed data to generate output data with reduced non-linearity.

3. 发明申请

US20170111013A1 VOLTAGE FOLLOWER CIRCUIT TO MITIGATE GAIN LOSS CAUSED BY FINITE OUTPUT IMPEDANCE OF TRANSISTORS 有权
公开(公告)号：US20170111013A1
公开(公告)日：2017-04-20
申请号：US15211100
申请日：2016-07-15
申请人： Signalchip Innovations Private Limited
发明人： Himamshu Gopalakrishna Khasnis , Anantha Melavarige Subraya , Naveen Mahadev
IPC分类号： H03F1/02 , H03F3/50
CPC分类号： H03F1/025 , H03F1/0266 , H03F3/50 , H03F3/505 , H03F2200/453 , H03F2200/555 , H03F2200/69
摘要： Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.

4. 发明授权

US09602240B1 Method and system for symbol level interference cancellation at a receiver for multiuser detection 有权
公开(公告)号：US09602240B1
公开(公告)日：2017-03-21
申请号：US15043803
申请日：2016-02-15
申请人： Signalchip Innovations Private Limited
发明人： Aravind Ganesan , Deepak Karkala , Rajesh Mundhada
IPC分类号： H04L1/00 , H04J11/00
CPC分类号： H04L1/0048 , H04B1/71072
摘要： Methods and systems of symbol level interference cancellation at a receiver for multiuser detection is provided. In an embodiment, the method includes performing an interference cancellation based decoding for a plurality of users through a plurality of iterations for generating a plurality of soft bit estimates for each of the users during each of the iterations. Each of the iterations involves sequential cancellation of each of the user signals for performing interference cancellation based decoding for each subsequent user other than a first user. The method also includes re-using the generated plurality of soft bit estimates for performing each subsequent iteration of the interference cancellation based decoding of the plurality of users. A plurality of soft bit estimates associated with each user generated during an (N−1)th iteration is re-used during an Nth iteration for the user, N being a whole number with a minimum value of 2.

5. 发明授权

US09584077B2 Impedance synthesis for optimum frequency response of a radio frequency (RF) amplifier 有权
标题翻译：用于射频（RF）放大器的最佳频率响应的阻抗综合
公开(公告)号：US09584077B2
公开(公告)日：2017-02-28
申请号：US14876577
申请日：2015-10-06
申请人： SIGNALCHIP INNOVATIONS PRIVATE LIMITED
发明人： Himamshu Gopalakrishna Khasnis , Naveen Mahadev
IPC分类号： H04B1/10 , H03F3/19 , H03F3/21 , H04L25/08
CPC分类号： H03F3/19 , H03F1/56 , H03F3/21 , H03F3/24 , H03F2200/294 , H03F2200/451 , H04B1/0458 , H04B1/0475 , H04B2001/0408 , H04L25/08
摘要： A method and system of synthesizing impedance in a radio frequency (RF) amplifier includes receiving a voltage signal at a passive mixer. The passive mixer down-converts the voltage signal into a baseband frequency. The method includes converting the voltage signal into a digital signal. Further, the method includes performing convolution of the digital signal with an impulse response. The impulse response is of a low Q impedance and is programmable. Furthermore the method includes generating a current signal based on output of the convolution. Furthermore the method includes performing up-conversion of the current signal in the passive mixer. The passive mixer performs impedance transformation of the low Q impedance. Moreover, the method includes providing the current signal via the passive mixer to synthesize desired impedance in the RF amplifier, thereby controlling frequency response of the RF amplifier.
摘要翻译：在射频（RF）放大器中合成阻抗的方法和系统包括在无源混频器处接收电压信号。无源混频器将电压信号下变频为基带频率。该方法包括将电压信号转换为数字信号。此外，该方法包括执行数字信号与脉冲响应的卷积。脉冲响应具有低Q阻抗，可编程。此外，该方法包括基于卷积的输出产生电流信号。此外，该方法包括在无源混频器中执行电流信号的上变频。无源混频器执行低Q阻抗的阻抗变换。此外，该方法包括通过无源混频器提供电流信号以在RF放大器中合成期望的阻抗，从而控制RF放大器的频率响应。

6. 发明授权

US09231710B2 System and method for reducing on-chip memory for frame buffer storage in WCDMA receiver 有权
公开(公告)号：US09231710B2
公开(公告)日：2016-01-05
申请号：US14154404
申请日：2014-01-14
申请人： Signalchip Innovations Private Limited
发明人： Himamshu Gopalakrishna Khasnis
IPC分类号： H04B14/04
CPC分类号： H04B14/046 , H04B1/707
摘要： A method of reducing an on-chip memory associated with storing frame buffer in WCDMA receiver includes obtaining, at a WCDMA front end receiver, an signal, transmitting, by an analog to digital convertor, input samples to a digital to digital sigma-delta converter, converting, by a sample rate convertor, a sampling rate associated with the input samples to a desired sampling rate for a rake receiver, quantizing, by the digital to digital sigma-delta converter, the input samples with a first number of bits to a converted data samples of a reduced number of bits, storing, at a memory unit, the converted data samples of the reduced number of bits, filtering the noise from the converted data samples to obtain a noise filtered converted data samples of the reduced number of bits, and decoding, at a WCDMA receiver processing unit, the noise filtered converted data samples over an entire radio frame.

7. 发明授权

US10164422B2 Protection circuit for low voltage devices driven by a high voltage circuit 有权
公开(公告)号：US10164422B2
公开(公告)日：2018-12-25
申请号：US15169148
申请日：2016-05-31
申请人： SIGNALCHIP INNOVATIONS PRIVATE LIMITED
发明人： Himamshu Gopalakrishna Khasnis , Nikhil Birur Gururaja Rao
IPC分类号： H02H3/20 , H02H1/00
摘要： A method and system for protecting low voltage devices driven by a high voltage circuit is disclosed. The method comprises monitoring an output voltage, from a high voltage block, to a low voltage block. The method further comprises comparing the output voltage with a range of voltages allowable for driving the low voltage block. The range of voltages may be pre-defined or dynamically determined. Furthermore, the method comprises operating a first set of switches and a second set of switches. The first set of switches are operated to feed voltage from the high voltage block to input of the low voltage block, and the second set of switches are operated to feed a plurality of reference voltages to the input of the low voltage block.

8. 发明授权

US09716472B2 Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors 有权
公开(公告)号：US09716472B2
公开(公告)日：2017-07-25
申请号：US15211100
申请日：2016-07-15
申请人： Signalchip Innovations Private Limited
发明人： Himamshu Gopalakrishna Khasnis , Anantha Melavarige Subraya , Naveen Mahadev
IPC分类号： H03F1/22 , H03F1/02 , H03F3/50
CPC分类号： H03F1/025 , H03F1/0266 , H03F3/50 , H03F3/505 , H03F2200/453 , H03F2200/555 , H03F2200/69
摘要： Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.

9. 发明申请

US20170103042A1 SYSTEM AND METHOD FOR OPTIMIZING MIXED RADIX FAST FOURIER TRANSFORM AND INVERSE FAST FOURIER TRANSFORM 审中-公开
公开(公告)号：US20170103042A1
公开(公告)日：2017-04-13
申请号：US15288548
申请日：2016-10-07
申请人： Signalchip Innovations Private Limited
发明人： Rajesh Mundhada , Pramod Udupa
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A system for implementing a mixed radix fast fourier transformation is disclosed. The system includes a data source 202, a digit-reverse address generator 204, a data memory 206, a register array 208, a control unit 210, a butterfly extraction unit 212, a twiddle factor generator 214, and a computation unit 216. The data source 202 provides input data. The digit reverse address generator 204 processes the input data (i) to generate a digit reverse index and performs a digits reverse address calculation. The data memory 206 stores the input data. The register array 208 includes one or more registers that are configured to cache multiple data words. The control unit 210 includes of identifying butterfly operations and generate addresses for fetching/storing data. The butterfly extraction unit 212 extracts data samples. The twiddle factor generator 214 generates and outputs a twiddle factors based on the current radix and radix configuration. The computation unit 216 performs twiddle factor multiplications and the butterfly operations for current radix.

10. 发明申请

US20170078048A1 METHOD AND SYSTEM FOR SYMBOL LEVEL INTERFERENCE CANCELLATION AT A RECEIVER FOR MULTIUSER DETECTION 有权
标题翻译：用于多路器检测的接收器上符号级别干扰消除的方法和系统
公开(公告)号：US20170078048A1
公开(公告)日：2017-03-16
申请号：US15043803
申请日：2016-02-15
申请人： Signalchip Innovations Private Limited
发明人： Aravind Ganesan , Deepak Karkala , Rajesh Mundhada
IPC分类号： H04L1/00 , H04J11/00
CPC分类号： H04L1/0048 , H04B1/71072
摘要： Methods and systems of symbol level interference cancellation at a receiver for multiuser detection is provided. In an embodiment, the method includes performing an interference cancellation based decoding for a plurality of users through a plurality of iterations for generating a plurality of soft bit estimates for each of the users during each of the iterations. Each of the iterations involves sequential cancellation of each of the user signals for performing interference cancellation based decoding for each subsequent user other than a first user. The method also includes re-using the generated plurality of soft bit estimates for performing each subsequent iteration of the interference cancellation based decoding of the plurality of users. A plurality of soft bit estimates associated with each user generated during an (N−1)th iteration is re-used during an Nth iteration for the user, N being a whole number with a minimum value of 2.
摘要翻译：提供了用于多用户检测的接收机处的符号级干扰消除的方法和系统。在一个实施例中，该方法包括通过多次迭代对多个用户执行基于干扰消除的解码，以在每个迭代期间为每个用户生成多个软比特估计。每个迭代涉及每个用户信号的顺序取消，用于对除了第一用户之外的每个后续用户执行基于干扰消除的解码。该方法还包括重新使用所生成的多个软比特估计，用于对多个用户的基于干扰消除的解码进行每个后续迭代。在用于用户的第N次迭代期间，重新使用在第（N-1）次迭代期间生成的与每个用户相关联的多个软比特估计，N是具有最小值2的整数。

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