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1. 发明授权

US08265216B2 Techniques for asynchronous data recovery 有权
标题翻译：异步数据恢复技术
公开(公告)号：US08265216B2
公开(公告)日：2012-09-11
申请号：US12252441
申请日：2008-10-16
申请人： Samir J Soni , Uday Padmanabhan , Michael D. Vicker
发明人： Samir J Soni , Uday Padmanabhan , Michael D. Vicker
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , H04L25/4902
摘要： A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.
摘要翻译：数据恢复电路包括脉冲宽度指示电路，边缘检测电路和第一存储器。脉冲宽度指示器电路被配置为在输入处接收数据流并在相应的输出处提供指示接收的数据流中的相应数据位的脉冲。边缘检测电路被配置为在相应的输入上接收来自脉冲宽度指示器电路的脉冲，并且响应于脉冲在相应的输出上提供指示相应数据位的逻辑电平的相应存储信号。第一存储器被配置为接收和存储相应的存储信号。

2. 发明申请

US20090175360A1 TECHNIQUES FOR COMPRESSING DIFFERENTIAL SAMPLES OF BANDWIDTH-LIMITED DATA TO REDUCE BANDWIDTH AND POWER CONSUMPTION BY AN INTERFACE 有权
标题翻译：用于压缩带宽有限数据的差分样本以减少接口带宽和功耗的技术
公开(公告)号：US20090175360A1
公开(公告)日：2009-07-09
申请号：US11970887
申请日：2008-01-08
申请人： Samir J. Soni , Pravin Pramakanthan , Clive K. Tang , Bing Xu
发明人： Samir J. Soni , Pravin Pramakanthan , Clive K. Tang , Bing Xu
IPC分类号： H04B1/66
CPC分类号： H03M7/30 , H04B1/66
摘要： Techniques and technologies are provided for compressing differential samples of bandwidth-limited data and coding the compressed differential samples to reduce bandwidth and power consumption when communicating bandwidth-limited data over a serial interface which couples one integrated circuit to another integrated circuit.
摘要翻译：提供了技术和技术，用于压缩带宽限制数据的差分样本，并对压缩的差分样本进行编码，以便在将一个集成电路耦合到另一个集成电路的串行接口上传送带宽限制的数据时，减少带宽和功耗。

3. 发明申请

US20090092214A1 CLOCK CIRCUIT WITH CLOCK TRANSFER CAPABILITY AND METHOD 有权
标题翻译：具有时钟传输能力和方法的时钟电路
公开(公告)号：US20090092214A1
公开(公告)日：2009-04-09
申请号：US11868711
申请日：2007-10-08
申请人： Srinivasa R. Bommareddy , Uday Padmanabhan , Samir J. Soni , Koichi E. Nomura , Nicholas F. Jungels , Vivek Bhan
发明人： Srinivasa R. Bommareddy , Uday Padmanabhan , Samir J. Soni , Koichi E. Nomura , Nicholas F. Jungels , Vivek Bhan
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , G06F1/04 , H04W88/02
摘要： An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.
摘要翻译：提供了一种包括多路复用器的设备，其被配置为提供从源时钟，目的地时钟和转换时钟中选择的输出时钟。该装置还包括：相位差计算模块，被配置为计算源时钟与目的地时钟之间的相位差;以及时钟生成模块，被配置为生成多个时钟。该装置还包括时钟选择模块，其被配置为选择多个时钟中的一个作为转换时钟;以及控制电路，被配置为提供：（1）信号到时钟选择模块，用于选择多个时钟中的一个作为转换基于源时钟和目的地时钟之间的相位差的时钟，以及（2）向多路复用器提供的信号作为源时钟，目的时钟或转换时钟之一的输出时钟。

4. 发明授权

US08204166B2 Clock circuit with clock transfer capability and method 有权
标题翻译：具有时钟传输能力和方法的时钟电路
公开(公告)号：US08204166B2
公开(公告)日：2012-06-19
申请号：US11868711
申请日：2007-10-08
申请人： Srinivasa R. Bommareddy , Uday Padmanabhan , Samir J. Soni , Koichi E. Nomura , Nicholas F. Jungels , Vivek Bhan
发明人： Srinivasa R. Bommareddy , Uday Padmanabhan , Samir J. Soni , Koichi E. Nomura , Nicholas F. Jungels , Vivek Bhan
IPC分类号： H03L7/06 , H04Q1/20
CPC分类号： H04L7/0012 , G06F1/04 , H04W88/02
摘要： An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.
摘要翻译：提供了一种包括多路复用器的设备，其被配置为提供从源时钟，目的地时钟和转换时钟中选择的输出时钟。该装置还包括：相位差计算模块，被配置为计算源时钟与目的地时钟之间的相位差;以及时钟生成模块，被配置为生成多个时钟。该装置还包括时钟选择模块，其被配置为选择多个时钟中的一个作为转换时钟;以及控制电路，被配置为提供：（1）信号到时钟选择模块，用于选择多个时钟中的一个作为转换基于源时钟和目的地时钟之间的相位差的时钟，以及（2）向多路复用器提供的信号作为源时钟，目的时钟或转换时钟之一的输出时钟。

5. 发明授权

US08630382B2 Asynchronous data recovery methods and apparatus 有权
标题翻译：异步数据恢复方法和装置
公开(公告)号：US08630382B2
公开(公告)日：2014-01-14
申请号：US12413101
申请日：2009-03-27
申请人： John R. Oakley , Uday Padmanabhan , Samir J. Soni
发明人： John R. Oakley , Uday Padmanabhan , Samir J. Soni
IPC分类号： H04L7/00 , H04L27/06 , H03L7/24
CPC分类号： H04L7/0338 , H04L7/0008 , H04L7/027 , H04L7/0276
摘要： Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations.
摘要翻译：数据恢复装置的实施例包括振荡器，边缘检测电路和数据存储。振荡器产生数据检测信号，其在串行比特流传送逻辑1的时间段期间传送第一系列脉冲，并且在串行比特流传送逻辑0的时间周期期间传送第二系列脉冲。边缘检测电路检测第一和第二脉冲序列的转移边缘，并产生数据存储信号，其包括第一系列脉冲中检测到的转变边缘的第一指示和第二系列脉冲中检测到的转移边缘的第二指示。响应于接收到第一指示，将逻辑1写入数据存储位位置的未屏蔽子集。响应于接收到第二指示，将逻辑0写入位掩码的位位置子集。

6. 发明申请

US20100098150A1 Techniques for Asynchronous Data Recovery 有权
标题翻译：异步数据恢复技术
公开(公告)号：US20100098150A1
公开(公告)日：2010-04-22
申请号：US12252441
申请日：2008-10-16
申请人： Samir J. Soni , Uday Padmanabhan , Michael D. Vicker
发明人： Samir J. Soni , Uday Padmanabhan , Michael D. Vicker
IPC分类号： H03K9/08
CPC分类号： H04L7/0338 , H04L25/4902
摘要： A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.
摘要翻译：数据恢复电路包括脉冲宽度指示电路，边缘检测电路和第一存储器。脉冲宽度指示器电路被配置为在输入处接收数据流并在相应的输出处提供指示接收的数据流中的相应数据位的脉冲。边缘检测电路被配置为在相应的输入上接收来自脉冲宽度指示器电路的脉冲，并且响应于脉冲在相应的输出上提供指示相应数据位的逻辑电平的相应存储信号。第一存储器被配置为接收和存储相应的存储信号。

7. 发明授权

US07835435B2 Techniques for compressing differential samples of bandwidth-limited data to reduce bandwidth and power consumption by an interface 有权
标题翻译：用于压缩带宽限制数据的差分样本以减少接口带宽和功耗的技术
公开(公告)号：US07835435B2
公开(公告)日：2010-11-16
申请号：US11970887
申请日：2008-01-08
申请人： Samir J. Soni , Pravin Pramakanthan , Clive K. Tang , Bing Xu
发明人： Samir J. Soni , Pravin Pramakanthan , Clive K. Tang , Bing Xu
IPC分类号： H04B1/66
CPC分类号： H03M7/30 , H04B1/66
摘要： Techniques and technologies are provided for compressing differential samples of bandwidth-limited data and coding the compressed differential samples to reduce bandwidth and power consumption when communicating bandwidth-limited data over a serial interface which couples one integrated circuit to another integrated circuit.
摘要翻译：提供了技术和技术，用于压缩带宽限制数据的差分样本，并对压缩的差分样本进行编码，以便在将一个集成电路耦合到另一个集成电路的串行接口上传送带宽限制的数据时，减少带宽和功耗。

8. 发明申请

US20100246735A1 ASYNCHRONOUS DATA RECOVERY METHODS AND APPARATUS 有权
标题翻译：异步数据恢复方法和设备
公开(公告)号：US20100246735A1
公开(公告)日：2010-09-30
申请号：US12413101
申请日：2009-03-27
申请人： John R. Oakley , Uday Padmanabhan , Samir J. Soni
发明人： John R. Oakley , Uday Padmanabhan , Samir J. Soni
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , H04L7/0008 , H04L7/027 , H04L7/0276
摘要： Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations.
摘要翻译：数据恢复装置的实施例包括振荡器，边缘检测电路和数据存储。振荡器产生数据检测信号，其在串行比特流传送逻辑1的时间段期间传送第一系列脉冲，并且在串行比特流传送逻辑0的时间周期期间传送第二系列脉冲。边缘检测电路检测第一和第二脉冲序列的转移边缘，并产生数据存储信号，其包括第一系列脉冲中检测到的转变边缘的第一指示和第二系列脉冲中检测到的转移边缘的第二指示。响应于接收到第一指示，将逻辑1写入数据存储位位置的未屏蔽子集。响应于接收到第二指示，将逻辑0写入位掩码的位位置子集。

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