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1. 发明授权

US09704766B2 Interposers of 3-dimensional integrated circuit package systems and methods of designing the same 有权
公开(公告)号：US09704766B2
公开(公告)日：2017-07-11
申请号：US13118201
申请日：2011-05-27
申请人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
发明人： Sandeep Kumar Goel , Mill-Jer Wang , Chung-Sheng Yuan , Tom Chen , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee
IPC分类号： H01L23/48 , H01L21/66 , H01L25/065
CPC分类号： H01L22/32 , H01L25/0655 , H01L2224/16225 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/00
摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

2. 发明授权

US09041411B2 Testing of an integrated circuit that contains secret information 有权
标题翻译：测试包含秘密信息的集成电路
公开(公告)号：US09041411B2
公开(公告)日：2015-05-26
申请号：US12063151
申请日：2006-08-09
申请人： Erik J. Marinissen , Sandeep Kumar Goel , Andre K. Nieuwland , Hubertus G. H. Vermuelen , Hendrikus P. E. Vranken
发明人： Erik J. Marinissen , Sandeep Kumar Goel , Andre K. Nieuwland , Hubertus G. H. Vermuelen , Hendrikus P. E. Vranken
IPC分类号： G01R31/02 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31719 , G01R31/318533
摘要： An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown. As a result, a person that does not know which fuse elements are first fuse elements and which are second fuse elements is presented with difficulties to restore the integrated circuit to a state where test access with the danger of access to the secured information is possible.
摘要翻译：集成电路（10）包括功能电路（12a-c），其包含必须防止未授权访问的信息。集成电路包括耦合到功能电路（12a-c）的测试访问电路（14,16）和耦合到测试访问电路（14,16）的多个熔丝元件（18）。保险丝元件（18）以仅在多个第一熔丝元件（18）处于吹制状态时通过测试存取电路（14,16）可一致地访问的电路配置连接并且多个的第二熔丝元件（18）处于未吹塑状态。结果，可以在选择性地吹扫所有第一熔丝元件（18）之后测试集成电路。在测试之后，至少部分第二熔丝元件（18）被吹塑。结果，不知道哪些熔丝元件是第一熔丝元件并且是第二熔丝元件的人被呈现难以将集成电路恢复到具有访问安全信息的危险的测试访问是可能的状态。

3. 发明授权

US08972918B2 System and method for functional verification of multi-die 3D ICs 有权
标题翻译：多芯片3D IC的功能验证系统和方法
公开(公告)号：US08972918B2
公开(公告)日：2015-03-03
申请号：US13359921
申请日：2012-01-27
申请人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
发明人： Stanley John , Ashok Mehta , Sandeep Kumar Goel , Kai-Yuan Ting
IPC分类号： G06F17/50
CPC分类号： G01R31/2886 , G01R31/318513
摘要： A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
摘要翻译：公开了一种用于多芯片3D IC的功能验证的系统和方法。该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

4. 发明授权

US08914692B2 DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips 有权
标题翻译：用于宽I / O DRAM的2.5D / 3D系统芯片的DRAM测试架构
公开(公告)号：US08914692B2
公开(公告)日：2014-12-16
申请号：US13484729
申请日：2012-05-31
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/28 , G11C29/56 , G11C11/40
CPC分类号： G11C29/56 , G11C11/40 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
摘要翻译： 2.5D或3D测试架构包括一个逻辑管芯和一个内存管芯。在2.5D架构中，逻辑管芯和存储器管芯安装在插入器上。在3D架构中，存储器管芯安装在逻辑管芯上。逻辑管芯包括用处理器封装件封装的控制逻辑。处理器包装器可以测试控制逻辑的组件。存储器管芯也安装在插入器上。存储器管芯包括动态随机存取存储器和通道选择/旁路逻辑。控制逻辑经由信道选择/旁路逻辑耦合到动态随机存取存储器，信道选择/旁路逻辑由处理器封装器控制。

5. 发明申请

US20130093452A1 PROBE CARD PARTITION SCHEME 有权
标题翻译：探针卡分割方案
公开(公告)号：US20130093452A1
公开(公告)日：2013-04-18
申请号：US13273633
申请日：2011-10-14
申请人： Sandeep Kumar GOEL , Mill-Jer WANG
发明人： Sandeep Kumar GOEL , Mill-Jer WANG
IPC分类号： G01R31/00
CPC分类号： G01R31/2889 , G01R1/0408 , G01R1/07342 , G01R31/31908
摘要： A method of probe card partitioning for testing an integrated circuit die includes providing a first probe card partition layout having a first number of distinct sections. Each distinct section uses a distinct probe card for testing. The first probe card partition layout is repartitioned into a second probe card partition layout having a second number of distinct sections. The second number is less than the first number.
摘要翻译：用于测试集成电路管芯的探针卡划分的方法包括提供具有第一数目不同部分的第一探针卡分区布局。每个不同的部分都使用不同的探针卡进行测试。第一探针卡分区布局被重新分配成具有第二数量不同部分的第二探针卡分区布局。第二个数字小于第一个数字。

6. 发明申请

US20130047046A1 DRAM TEST ARCHITECTURE FOR WIDE I/O DRAM BASED 2.5D/3D SYSTEM CHIPS 有权
标题翻译：用于基于I / O DRAM的2.5D / 3D系统芯片的DRAM测试架构
公开(公告)号：US20130047046A1
公开(公告)日：2013-02-21
申请号：US13484729
申请日：2012-05-31
申请人： Sandeep Kumar GOEL
发明人： Sandeep Kumar GOEL
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G11C29/56 , G11C11/40 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
摘要翻译： 2.5D或3D测试架构包括一个逻辑管芯和一个内存管芯。在2.5D架构中，逻辑管芯和存储器管芯安装在插入器上。在3D架构中，存储器管芯安装在逻辑管芯上。逻辑管芯包括用处理器封装件封装的控制逻辑。处理器包装器可以测试控制逻辑的组件。存储器管芯也安装在插入器上。存储器管芯包括动态随机存取存储器和通道选择/旁路逻辑。控制逻辑经由信道选择/旁路逻辑耦合到动态随机存取存储器，信道选择/旁路逻辑由处理器封装器控制。

7. 发明授权

US08873320B2 DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips 有权
标题翻译：用于宽I / O DRAM的2.5D / 3D系统芯片的DRAM修复架构
公开(公告)号：US08873320B2
公开(公告)日：2014-10-28
申请号：US13489199
申请日：2012-06-05
申请人： Sandeep Kumar Goel , Tze-Chiang Huang
发明人： Sandeep Kumar Goel , Tze-Chiang Huang
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C29/816 , H01L2224/13025 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2224/17181 , H01L2224/81193 , H01L2924/1431 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311
摘要： A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.
摘要翻译： 2.5D或3D维修架构包括一个逻辑管芯和一个内存管芯。在2.5D架构中，逻辑管芯和存储器管芯安装在插入器上。在3D架构中，存储器管芯安装在逻辑管芯上。该逻辑具有包含处理器包装器的控制逻辑。处理器包装器可以测试控制逻辑的组件。控制逻辑还包括宽输入/输出控制器，内置维修分析器（BIRA）和维修控制器。利用修复架构的方法提供修复存储器件的故障列和行。

8. 发明授权

US08686570B2 Multi-dimensional integrated circuit structures and methods of forming the same 有权
标题翻译：多维集成电路结构及其形成方法
公开(公告)号：US08686570B2
公开(公告)日：2014-04-01
申请号：US13354967
申请日：2012-01-20
申请人： Mark Semmelmeyer , Sandeep Kumar Goel
发明人： Mark Semmelmeyer , Sandeep Kumar Goel
IPC分类号： H01L23/52
CPC分类号： H05K1/0201 , H01L21/561 , H01L22/22 , H01L23/3128 , H01L23/5384 , H01L23/5385 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/81005 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/12042 , H01L2924/1461 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H05K1/11 , H05K1/144 , H05K3/46 , H05K2201/10734 , Y10T29/49124 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A structure comprises a first die, a second die, an interposer, a third die, and a fourth die. The first die and the second die each have a first surface and a second surface. First conductive connectors are coupled to the first surfaces of the first and second dies, and second conductive connectors are coupled to the second surfaces of the first and second dies. The interposer is over the first and second dies. A first surface of the interposer is coupled to the first conductive connectors, and a second surface of the interposer is coupled to third conductive connectors. The third and fourth dies are over the interposer and are coupled to the third conductive connectors. The first die is communicatively coupled to the second die through the interposer, and/or the third die is communicatively coupled to the fourth die through the interposer.
摘要翻译：一种结构包括第一模具，第二模具，插入件，第三模具和第四模具。第一模具和第二模具各自具有第一表面和第二表面。第一导电连接器耦合到第一和第二模具的第一表面，并且第二导电连接器耦合到第一和第二模具的第二表面。内插器超过了第一和第二个模具。插入器的第一表面耦合到第一导电连接器，并且插入器的第二表面耦合到第三导电连接器。第三和第四管芯在插入件上方并且耦合到第三导电连接器。第一裸片通过插入器与第二裸片通信地耦合，和/或第三裸片通过插入器通信地耦合到第四裸片。

9. 发明申请

US20130326463A1 Method to Determine Optimal Micro-Bump-Probe Pad Pairing for Efficient PGD Testing in Interposer Designs 有权
标题翻译：确定内插器设计中高效PGD测试的最佳微型碰撞探针焊盘配对的方法
公开(公告)号：US20130326463A1
公开(公告)日：2013-12-05
申请号：US13484531
申请日：2012-05-31
申请人： Yi-Lin Chuang , Cheng-Pin Chiu , Ching-Fang Chen , Ji-Jan Chen , Sandeep Kumar Goel , Yun-Han Lee , Charles C.C. Liu
发明人： Yi-Lin Chuang , Cheng-Pin Chiu , Ching-Fang Chen , Ji-Jan Chen , Sandeep Kumar Goel , Yun-Han Lee , Charles C.C. Liu
IPC分类号： G06F17/50
CPC分类号： G01R31/2889
摘要： The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.
摘要翻译：本公开涉及一种将探针焊盘布置到插入件的微凸块的方法。提供具有目标微凸块和探针垫的插入件。探针垫最初未分配。获得目标微凸点位置和探针垫位置。获得从探针焊盘到目标微凸块的可能路线分配。至少部分地根据目标微凸块位置和探针垫位置为可能的路线分配开发成本。根据成本从可能的分配中选择最终作业。

10. 发明授权

US08561001B1 System and method for testing stacked dies 有权
标题翻译：堆叠模具测试系统和方法
公开(公告)号：US08561001B1
公开(公告)日：2013-10-15
申请号：US13546033
申请日：2012-07-11
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： G06F17/50 , G06F12/00 , G06F13/38 , G11C11/4063 , G11C11/4193 , G11C16/32 , G11C7/22 , G11C8/18 , G11B19/04 , G06F13/40 , G11C11/419
CPC分类号： H03K5/04 , G06F12/00 , G06F13/4004 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G11B19/04 , G11C7/222 , G11C8/18 , G11C11/4063 , G11C11/419 , G11C16/32 , G11C29/26 , G11C29/44 , G11C29/50012
摘要： Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.
摘要翻译：公开了用于在一堆模具中测试模具并插入修复电路的系统和方法，该修复电路在使能时补偿管芯堆叠中的延迟缺陷。确定晶片内和模间松弛值以确定模具堆叠中的哪个模具或模具将从插入修复电路中受益。

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