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1. 发明授权

US09070684B2 Integrated circuit power grid with improved routing resources and bypass capacitance 有权
标题翻译：集成电路电网具有改进的路由资源和旁路电容
公开(公告)号：US09070684B2
公开(公告)日：2015-06-30
申请号：US13460291
申请日：2012-04-30
申请人： Scott A. Segan , Scott T. Van Horn , Gary E. Hall , Matthew J. Gehman , Richard Muscavage
发明人： Scott A. Segan , Scott T. Van Horn , Gary E. Hall , Matthew J. Gehman , Richard Muscavage
IPC分类号： H01L27/10 , H01L23/52 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5223 , H01L23/5283 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.
摘要翻译：集成电路电网提供改进的路由资源和旁路电容。用于集成电路的电网包括具有多个金属迹线的多个厚金属层，其中至少一个厚金属层具有比针对给定集成电路制造的设计规则允许的基本最大间距更低的间距技术。用于集成电路的电网还可以包括具有多个金属迹线的多个薄金属层，其中不同金属薄层上的多个金属迹线通过至少一个通孔连接，其中至少一个通孔是在与一个或多个另外的金属级别的电源相比不同的电源电压的至少一个细金属电平上基本上被金属迹线包围。通孔可以定位在例如给定的标准单元行和给定的垂直带的交点处。

2. 发明授权

US08315830B2 On-chip variation, speed and power regulator 失效
标题翻译：片内变化，速度和功率调节器
公开(公告)号：US08315830B2
公开(公告)日：2012-11-20
申请号：US11970597
申请日：2008-01-08
申请人： Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： G06F11/30 , G06F11/00
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.
摘要翻译：使用设置在芯片的各个区域的一个或多个速度测量元件（例如环形振荡器）测量集成电路芯片的操作速度。每个速度测量元件可以包括几个环形振荡器，每个环形振荡器对应于不同的技术阈值电压。从速度测量元件收集的速度测量数据可用于确定片上变化（OCV）。芯片本身或芯片外部的电路可以根据速度测量数据调整芯片工作参数，如核心电压或时钟速度。速度测量数据可以通过JTAG引脚或与外部主机的接口读出芯片。

3. 发明申请

US20090177442A1 ON-CHIP VARIATION, SPEED AND POWER REGULATOR 失效
标题翻译：片上变速，速度和功率调节器
公开(公告)号：US20090177442A1
公开(公告)日：2009-07-09
申请号：US11970597
申请日：2008-01-08
申请人： Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.
摘要翻译：使用设置在芯片的各个区域的一个或多个速度测量元件（例如环形振荡器）测量集成电路芯片的操作速度。每个速度测量元件可以包括几个环形振荡器，每个环形振荡器对应于不同的技术阈值电压。从速度测量元件收集的速度测量数据可用于确定片上变化（OCV）。芯片本身或芯片外部的电路可以根据速度测量数据调整芯片工作参数，如核心电压或时钟速度。速度测量数据可以通过JTAG引脚或与外部主机的接口读出芯片。

4. 发明授权

US06465884B1 Semiconductor device with variable pin locations 有权
标题翻译：具有可变引脚位置的半导体器件
公开(公告)号：US06465884B1
公开(公告)日：2002-10-15
申请号：US09578082
申请日：2000-05-24
申请人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
发明人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
IPC分类号： H01L2940
CPC分类号： G11C5/066 , G11C29/1201
摘要： An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.
摘要翻译：一种包括逻辑电路，多个引脚和将逻辑电路耦合到多个引脚的接口单元的半导体器件，其中接口单元允许任何引脚耦合到逻辑电路的任何部分。半导体器件提供了一种模板，通过该模板可以制造具有不同引脚分配的许多不同类型的半导体器件，而不需要改变生产掩模。

5. 发明授权

US06438672B1 Memory aliasing method and apparatus 有权
标题翻译：存储器混叠方法和装置
公开(公告)号：US06438672B1
公开(公告)日：2002-08-20
申请号：US09327157
申请日：1999-06-03
申请人： Frederick Harrison Fischer , Vladimir Sindalovsky , Scott A. Segan
发明人： Frederick Harrison Fischer , Vladimir Sindalovsky , Scott A. Segan
IPC分类号： G06F1200
CPC分类号： G06F12/0638 , G06F12/0862
摘要： A flexible memory overlaying apparatus and method stores repeatedly referenced information, e.g, common global variables, common code segments, interrupt service routines, and/or any other user or system definable information, in spare addressable circuits accessed by a memory aliasing or overlaying module. The memory aliasing module monitors (or snoops) memory access by a processor to redirect access to certain appropriate addressable circuits to provide faster access to the information than would be available in an access made from main memory. The memory overlaying apparatus and method provides an efficient context switching, e.g., during an interrupt, enables a reduction in the size of instruction code requirements, and helps avoid the occurrences of cache misses, and/or thrashing between cached pages.
摘要翻译：灵活的存储器重叠装置和方法在由存储器混叠或覆盖模块访问的备用可寻址电路中重复引用信息，例如公共全局变量，公共代码段，中断服务程序和/或任何其他用户或系统可定义信息。存储器混叠模块通过处理器监视（或窥探）存储器访问以将访问重定向到某些适当的可寻址电路，以提供比从主存储器进行的访问中可用的信息更快的访问。存储器重叠装置和方法提供了有效的上下文切换，例如在中断期间，能够减少指令代码要求的大小，并且有助于避免高速缓存未命中的发生和/或缓存的页面之间的抖动。

6. 发明授权

US5945850A Edge signal restoration circuit and method 失效
标题翻译：边沿信号恢复电路及方法
公开(公告)号：US5945850A
公开(公告)日：1999-08-31
申请号：US963063
申请日：1997-11-03
申请人： Scott A. Segan , Richard Muscavage
发明人： Scott A. Segan , Richard Muscavage
IPC分类号： H03K5/12 , H03K5/1534 , H03K5/19
CPC分类号： H03K5/1534 , H03K5/12
摘要： An edge signal restoration circuit and method to enhance an edge of a signal decreases a rise and fall time of a propagating signal during transitions between logic states. The edge signal restoration circuit includes a first circuit to detect an edge of an input signal and to output a detection signal, and a second circuit to drive a next state of the input signal in response to the detection signal at approximately the same time as the first circuit detects the edge of the input signal. The edge signal restoration method detects a transition of the signal between a current state and a next state, and drives the next state onto the signal during its transition to that next state.
摘要翻译：用于增强信号边沿的边缘信号恢复电路和方法在逻辑状态之间的转换期间降低了传播信号的上升和下降时间。边沿信号恢复电路包括：第一电路，用于检测输入信号的边沿并输出检测信号;以及第二电路，用于响应于大致相同的时间响应于检测信号来驱动输入信号的下一个状态第一电路检测输入信号的边沿。边缘信号恢复方法检测信号在当前状态和下一状态之间的转变，并且在转换到下一状态期间将下一状态驱动到该信号上。

7. 发明授权

US08680907B2 Delay circuit having reduced duty cycle distortion 有权
标题翻译：具有减小占空比失真的延迟电路
公开(公告)号：US08680907B2
公开(公告)日：2014-03-25
申请号：US12033567
申请日：2008-02-19
申请人： James D. Chlipala , Scott A. Segan
发明人： James D. Chlipala , Scott A. Segan
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00136 , H03K2005/00234
摘要： A delay circuit having reduced duty cycle distortion is provided. The delay circuit includes a plurality of delay elements connected together in a series configuration. Each of the delay elements has a prescribed delay associated therewith. The delay circuit further includes a controller connected to respective outputs of the delay elements. The controller is configured such that signal paths between the respective outputs of the delay elements and an output of the controller have delays that are substantially the same relative to one another. Each of the signal paths has a tri-statable switching element associated therewith.
摘要翻译：提供具有减小的占空比失真的延迟电路。延迟电路包括以串联配置连接在一起的多个延迟元件。每个延迟元件具有与之相关联的规定延迟。延迟电路还包括连接到延迟元件的相应输出的控制器。控制器被配置为使得延迟元件的相应输出和控制器的输出之间的信号路径具有相对于彼此基本相同的延迟。每个信号路径都具有与其相关联的三态开关元件。

8. 发明授权

US09158359B2 Adaptive voltage scaling using a serial interface 有权
标题翻译：使用串行接口进行自适应电压调整
公开(公告)号：US09158359B2
公开(公告)日：2015-10-13
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： H02J1/00 , G06F1/32
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译：自适应电压缩放系统包括第一和第二装置。第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。第一和第二器件从电压调节器接收电压。还公开了相应的方法和计算机可读介质。

9. 发明申请

US20130249290A1 Adaptive Voltage Scaling Using a Serial Interface 有权
标题翻译：使用串行接口的自适应电压调节
公开(公告)号：US20130249290A1
公开(公告)日：2013-09-26
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： H02J1/00
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译：自适应电压缩放系统包括第一和第二装置。第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。第一和第二器件从电压调节器接收电压。还公开了相应的方法和计算机可读介质。

10. 发明授权

US08350589B2 Critical-path circuit for performance monitoring 失效
标题翻译：用于性能监控的关键路径电路
公开(公告)号：US08350589B2
公开(公告)日：2013-01-08
申请号：US12738931
申请日：2009-01-27
申请人： James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： H03K19/00 , G01R31/28
CPC分类号： H03K19/00 , G01R31/31858 , H03K5/135
摘要： An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
摘要翻译：公开了一种具有用于监视具有目标定时裕度的关键路径中的定时的监视器电路的集成电路。监视器电路具有两个移位寄存器，其中之一包括向接收信号施加延迟值的延迟元件。两个移位寄存器的输入形成能够接收输入信号的信号输入节点。监视器电路还具有一个具有输出和至少两个输入的逻辑门，每个输入连接到两个移位寄存器的相应输出之一。逻辑门的输出指示目标定时裕度是否满足或不满足。

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