会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 2. 发明授权
      US08026749B2 Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit 失效
    • Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit
    • 锁相环电路，锁相环电路的操作方法和包括锁相环电路的半导体存储器件
    • US08026749B2
    • 2011-09-27
    • US12591399
    • 2009-11-18
    • Seungjun Bae , Young-Sik Kim , Sanghyup Kwak
    • Seungjun Bae , Young-Sik Kim , Sanghyup Kwak
    • H03L7/06
    • H03L7/081 , H03L7/07 , H03L7/087 , H03L7/0891
    • A phase locked loop circuit includes a delay compensation circuit and a phase change circuit. The delay compensation circuit is adapted to generate a delay clock signal by delaying a phase of a first output clock signal by a second phase, the phase of the first output clock signal having a phase leading a phase of an input clock signal by a first phase, and the second phase corresponding to a delay compensation time greater than a period of the input clock signal and greater than the first phase. The phase change circuit is adapted to change the second phase to the first phase and to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal in response to the first phase, wherein the first phase is a phase corresponding to a remainder time resulting from the delay compensation time being divided by the period of the input clock, and wherein the quotient is an integer.
    • 锁相环电路包括延迟补偿电路和相变电路。 延迟补偿电路适于通过将第一输出时钟信号的相位延迟第二相来产生延迟时钟信号，第一输出时钟信号的相位具有将输入时钟信号的相位引导到第一相位的相位 ，并且第二相位对应于大于输入时钟信号的周期的延迟补偿时间并且大于第一相位。 相变电路适于将第二相位改变为第一相位，并响应于第一相位产生具有与输入时钟信号的相位同步的相位的反馈时钟信号，其中第一相位是对应于 由延迟补偿时间产生的剩余时间除以输入时钟的周期，并且其中商是整数。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US07778097B2 AC coupling circuits including resistive feedback and related methods and devices 有权
    • AC coupling circuits including resistive feedback and related methods and devices
    • AC耦合电路包括电阻反馈和相关方法和器件
    • US07778097B2
    • 2010-08-17
    • US12142085
    • 2008-06-19
    • Daehyun Chung , Sihong Kim , Jingook Kim , Kwangil Park , Seungjun Bae , Jaehyung Lee
    • Daehyun Chung , Sihong Kim , Jingook Kim , Kwangil Park , Seungjun Bae , Jaehyung Lee
    • G11C7/00
    • H03K19/0175 , H03F2203/45522
    • An integrated circuit device may include an amplifier having an amplifier input configured to receive an input signal with the amplifier being configured to provide an amplifier output signal at an amplifier output responsive to the input signal received at the amplifier input. A capacitor may be coupled to the amplifier output, and a buffer may be coupled to the capacitor so that the capacitor is coupled in series between the amplifier output and an input of the buffer with an output of the buffer being coupled to a buffered signal terminal. A variable resistive feedback circuit may be coupled between the input and output of the buffer with the variable resistive feed back circuit providing a variable resistance between the input and output of the buffer. A feedback resistance controller may be coupled to the variable resistive feedback circuit with the feedback resistance controller being configured to select a first resistance for the variable resistive feedback circuit for a first frequency of the input signal and to select a second resistance for the variable resistive feedback circuit for a second frequency of the input signal different than the first frequency with the first and second resistances being different.
    • 集成电路装置可以包括具有放大器输入的放大器，该放大器输入被配置为接收输入信号，放大器被配置为响应于在放大器输入处接收的输入信号而在放大器输出处提供放大器输出信号。 电容器可以耦合到放大器输出，并且缓冲器可以耦合到电容器，使得电容器串联耦合在放大器输出和缓冲器的输入之间，缓冲器的输出耦合到缓冲信号端子 。 可变电阻反馈电路可以在缓冲器的输入和输出之间耦合，其中可变电阻反馈电路在缓冲器​​的输入和输出之间提供可变电阻。 反馈电阻控制器可以耦合到可变电阻反馈电路，反馈电阻控制器被配置为为输入信号的第一频率选择用于可变电阻反馈电路的第一电阻，并为可变电阻反馈选择第二电阻 电路，用于与第一和第二电阻不同的第一频率的输入信号的第二频率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20100123498A1 Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit 失效
    • Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit
    • 锁相环电路，锁相环电路的操作方法和包括锁相环电路的半导体存储器件
    • US20100123498A1
    • 2010-05-20
    • US12591399
    • 2009-11-18
    • Seungjun Bae , Young-Sik Kim , Sanghyup Kwak
    • Seungjun Bae , Young-Sik Kim , Sanghyup Kwak
    • H03L7/06
    • H03L7/081 , H03L7/07 , H03L7/087 , H03L7/0891
    • A phase locked loop circuit includes a delay compensation circuit and a phase change circuit. The delay compensation circuit is adapted to generate a delay clock signal by delaying a phase of a first output clock signal by a second phase, the phase of the first output clock signal having a phase leading a phase of an input clock signal by a first phase, and the second phase corresponding to a delay compensation time greater than a period of the input clock signal and greater than the first phase. The phase change circuit is adapted to change the second phase to the first phase and to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal in response to the first phase, wherein the first phase is a phase corresponding to a remainder time resulting from the delay compensation time being divided by the period of the input clock, and wherein the quotient is an integer.
    • 锁相环电路包括延迟补偿电路和相变电路。 延迟补偿电路适于通过将第一输出时钟信号的相位延迟第二相来产生延迟时钟信号，第一输出时钟信号的相位具有将输入时钟信号的相位引导到第一相位的相位 ，并且第二相位对应于大于输入时钟信号的周期的延迟补偿时间并且大于第一相位。 相变电路适于将第二相位改变为第一相位，并响应于第一相位产生具有与输入时钟信号的相位同步的相位的反馈时钟信号，其中第一相位是对应于 由延迟补偿时间产生的剩余时间除以输入时钟的周期，并且其中商是整数。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US08055930B2 Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices 有权
    • Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices
    • 内部时钟信号发生电路包括分频和相位控制及相关方法，系统和设备
    • US08055930B2
    • 2011-11-08
    • US12198245
    • 2008-08-26
    • Seungjun Bae , JinGook Kim , Kwangil Park , Daehyun Chung
    • Seungjun Bae , JinGook Kim , Kwangil Park , Daehyun Chung
    • G06F1/00 , G06F1/04 , H03L7/00
    • G06F1/12
    • An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.
    • 集成电路装置可以包括被配置为接收具有主时钟频率的主时钟信号的主时钟信号输入焊盘，被配置为接收具有大于主时钟​​频率的高速时钟频率的高速时钟信号的高速时钟信号输入焊盘 时钟频率，分频器和相位控制器。 分频器可以被配置为响应于高速时钟信号产生多个初步内部时钟信号，其中每个初步内部时钟信号具有相同的主时钟频率和不同的相位。 相位控制器可以被配置为选择具有与主时钟信号的相位最紧密匹配的相位的初步内部时钟信号之一，并且将初步内部时钟信号转换为内部时钟信号，使得初步内部时钟信号具有 与主时钟信号的相位最接近的相位被转换为主要内部时钟信号，使得内部时钟信号具有主时钟频率。 还讨论了相关方法，系统和设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明申请
      US20090100285A1 Internal Clock Signal Generating Circuits Including Frequency Division and Phase Control and Related Methods, Systems, and Devices 有权
    • Internal Clock Signal Generating Circuits Including Frequency Division and Phase Control and Related Methods, Systems, and Devices
    • 内部时钟信号发生电路包括频分和相位控制及相关方法，系统和设备
    • US20090100285A1
    • 2009-04-16
    • US12198245
    • 2008-08-26
    • Seungjun Bae , JinGook Kim , Kwangil Park , Daehyun Chung
    • Seungjun Bae , JinGook Kim , Kwangil Park , Daehyun Chung
    • G06F1/12
    • G06F1/12
    • An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.
    • 集成电路装置可以包括被配置为接收具有主时钟频率的主时钟信号的主时钟信号输入焊盘，被配置为接收具有大于主时钟​​频率的高速时钟频率的高速时钟信号的高速时钟信号输入焊盘 时钟频率，分频器和相位控制器。 分频器可以被配置为响应于高速时钟信号产生多个初步内部时钟信号，其中每个初步内部时钟信号具有相同的主时钟频率和不同的相位。 相位控制器可以被配置为选择具有与主时钟信号的相位最紧密匹配的相位的初步内部时钟信号之一，并且将初步内部时钟信号转换为内部时钟信号，使得初步内部时钟信号具有 与主时钟信号的相位最接近的相位被转换为主要内部时钟信号，使得内部时钟信号具有主时钟频率。 还讨论了相关方法，系统和设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号