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    • 2. 发明授权
    • Correlation-based branch prediction in digital computers
    • 数字计算机中相关分支预测
    • US5553253A
    • 1996-09-03
    • US221283
    • 1994-03-30
    • Shien-Tai PanKimming So
    • Shien-Tai PanKimming So
    • G06F9/38G06F9/32
    • G06F9/3848
    • Method and apparatus for predicting the outcome of branch instructions subject to execution in a multiple processor digital computer. Pipelining is a popular technique to accelerate the data processing rate of modern computers, and in particular the RISC architecture class of workstations. Accurate prediction of branch instructions is exceptionally important to the efficient use of pipelines, in that erroneous predictions require both the purge and reload of all affected processor pipelines. According to the present invention, branch prediction is based upon a correlation between a history of successive prior branches and a specified branch instruction. In a preferred practice, a branch prediction table is created. The fields in the table are derived and thereafter updated based upon the correlated combination of outcomes from prior branches and the branch address under consideration.
    • 用于预测在多处理器数字计算机中执行的分支指令的结果的方法和装置。 流水线是加速现代计算机的数据处理速度,特别是RISC架构类工作站的流行技术。 分支指令的准确预测对于有效利用管道是非常重要的,因为错误的预测要求所有受影响的处理器管线的清除和重新加载。 根据本发明,分支预测基于连续的现有分支的历史与指定分支指令之间的相关性。 在优选的实践中,创建分支预测表。 表格中的字段是根据现有分支结果与所考察的分支地址的相关组合而得出的。
    • 10. 发明申请
    • MEMORY ACCESS SYSTEMS FOR CONFIGURING WAYS AS CACHE OR DIRECTLY ADDRESSABLE MEMORY
    • 用于配置方式的存储器访问系统作为缓存或直接寻址的存储器
    • US20080201528A1
    • 2008-08-21
    • US12107965
    • 2008-04-23
    • Ting-Cheng HsuYen-Yu LinShien-Tai Pan
    • Ting-Cheng HsuYen-Yu LinShien-Tai Pan
    • G06F12/00
    • G06F12/0653G06F12/0895Y02D10/13
    • A memory system is provided. A processor provides a data access address. A memory device includes a predetermined number of ways. The processor selectively configures a selected number less than or equal to the predetermined number of the ways as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by memory configuration information. A memory controller determines the data access address corresponding to the cacheable region or the directly addressable region, selects only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selects only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region. A configuration controller monitors the status of the ways and adjusting the memory configuration information according to the status of the ways.
    • 提供了一种存储系统。 处理器提供数据访问地址。 存储器装置包括预定数量的方式。 处理器有选择地将属于可高速缓存区域的高速缓冲存储器的预定数目的小于或等于预定数量的选择性配置,并且通过存储器配置信息将属于可直接寻址区域的直接可寻址存储器的剩余方式配置。 存储器控制器确定与可高速缓存区域或直接可寻址区域相对应的数据访问地址,当数据访问地址对应于直接可寻址区域时,仅选择对应于数据访问地址的直接可寻址区域中的方式,并且仅选择 当数据访问地址对应于可缓存区域时属于可缓存区域的方式。 配置控制器根据方式的状态监控方式的状态并调整内存配置信息。