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1. 发明申请

US20120246602A1 METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：制作图案的方法，制造半导体器件的方法和计算机程序产品
公开(公告)号：US20120246602A1
公开(公告)日：2012-09-27
申请号：US13237663
申请日：2011-09-20
申请人： Sachiko Kobayashi , Satoshi Tanaka , Shigeki Nojima , Kazuhiro Takahata
发明人： Sachiko Kobayashi , Satoshi Tanaka , Shigeki Nojima , Kazuhiro Takahata
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , H01L27/0207
摘要： An embodiment provides a method of preparing a pattern. In the pattern preparing method, when mask patterns corresponding to on-substrate patterns are prepared to form the on-substrate patterns corresponding to design patterns, the mask patterns are prepared based on a correlation which needs to be satisfied between the design patterns so that a relation which same the correlation can be satisfied between the mask patterns corresponding to the design patterns.
摘要翻译：实施例提供了一种制备图案的方法。在图案制作方法中，当准备对应于衬底图案的掩模图案以形成与设计图案相对应的衬底上图案时，基于需要在设计图案之间满足的相关性来准备掩模图案，使得在与设计图案对应的掩模图案之间可以满足相关性的关系。

2. 发明授权

US07890908B2 Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device 有权
标题翻译：用于验证掩模图案数据的方法，用于制造掩模的方法，掩模图案验证程序以及用于制造半导体器件的方法
公开(公告)号：US07890908B2
公开(公告)日：2011-02-15
申请号：US11472441
申请日：2006-06-22
申请人： Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
发明人： Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is prepared. Mask pattern data on a pattern of a mask used in order to produce the design circuit pattern is prepared. A circuit pattern which is to be obtained by processing a film using the pattern of the mask indicated by the mask pattern data is acquired. Circuit data on a circuit realized by at least a first part of the circuit pattern is produced. A circuit mismatch part where the circuit data and a part of the design circuit data which corresponds to the first part of the circuit pattern do not match up is detected.
摘要翻译：一种验证掩模图案数据的方法包括：在设计电路上准备设计电路数据，实现所需的电气操作。制备具有实现半导体衬底上的设计电路的结构的设计电路图案的数据。准备用于产生设计电路图案的掩模图形上的掩模图案数据。获取通过使用由掩模图案数据指示的掩模的图案来处理胶片而获得的电路图案。产生由电路图案的至少第一部分实现的电路上的电路数据。检测与电路图案的第一部分对应的电路数据和设计电路数据的一部分不匹配的电路失配部。

3. 发明申请

US20110029938A1 PATTERN CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：图案创造方法，计算机程序产品和制造半导体器件的方法
公开(公告)号：US20110029938A1
公开(公告)日：2011-02-03
申请号：US12843314
申请日：2010-07-26
申请人： Shigeki NOJIMA , Masahiro MIYAIRI
发明人： Shigeki NOJIMA , Masahiro MIYAIRI
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： According to one embodiment, a pattern creating method includes: calculating, from pattern data on which a circuit pattern formed on a substrate and an auxiliary pattern not formed on the substrate are arranged, a first feature value of a first pattern edge of a circuit pattern affected by the auxiliary pattern and a second feature value of a second pattern edge connected to the first pattern edge; and arranging, when a relation between the feature values does not have a desired relation corresponding to the circuit pattern, the auxiliary pattern such that the relation between the feature values has the relation corresponding to a shape of the circuit pattern.
摘要翻译：根据一个实施例，图案生成方法包括：从形成在基板上的电路图案和未形成在基板上的辅助图案的图案数据计算电路图案的第一图案边缘的第一特征值受辅助图案的影响和连接到第一图案边缘的第二图案边缘的第二特征值; 并且当所述特征值之间的关系不具有与所述电路图案对应的期望关系时，所述辅助图案使得所述特征值之间的关系具有与所述电路图案的形状相对应的关系。

4. 发明授权

US07571417B2 Method and system for correcting a mask pattern design 失效
标题翻译：用于校正掩模图案设计的方法和系统
公开(公告)号：US07571417B2
公开(公告)日：2009-08-04
申请号：US11012494
申请日：2004-12-16
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合在可变范围内或在相应的可变范围内。位置偏移是第一点与评价点之间的位移。该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

5. 发明申请

US20090077530A1 DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM 失效
公开(公告)号：US20090077530A1
公开(公告)日：2009-03-19
申请号：US12269705
申请日：2008-11-12
申请人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
发明人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

6. 发明申请

US20090077529A1 DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM 审中-公开
标题翻译：设计图案校正方法，设计图案形成方法，过程逼近效应校正方法，半导体器件和设计图案校正程序
公开(公告)号：US20090077529A1
公开(公告)日：2009-03-19
申请号：US12269687
申请日：2008-11-12
申请人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
发明人： TOSHIYA KOTANI , Shigeki Nojima , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
摘要翻译：公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度，确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式两个提取的顶点的位置彼此相对。

7. 发明授权

US07213226B2 Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and software product for executing the correction method 失效
标题翻译：使用修正方法制作的OPC，掩模和半导体器件的图案尺寸校正方法和验证方法，以及执行校正方法的系统和软件产品
公开(公告)号：US07213226B2
公开(公告)日：2007-05-01
申请号：US10920397
申请日：2004-08-18
申请人： Toshiya Kotani , Shigeki Nojima
发明人： Toshiya Kotani , Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.
摘要翻译：一种当在晶片上形成设计图案时通过使用OPC来校正精加工图案尺寸的方法，包括选择和确定包括在设计图案中的第一设计图案; 当在晶片上形成第一设计图案时，获取第一精加工图案尺寸的测量值; 通过使用所述第一完成图案维度来确定第一计算模型; 从除了第一设计图案之外的设计图案中选择和确定第二设计图案; 通过使用第一计算模型执行第一模拟，以及当在晶片上形成第二设计图案时计算第二精加工图案尺寸; 通过使用第一和第二完成图案尺寸，确定用于执行比第一模拟更快的第二模拟的第二计算模型; 以及通过使用所述第二计算模型执行所述第二模拟，以及计算除了所述第一和第二设计图案之外的所述设计图案的第三设计图案的第三精加工图案尺寸。

8. 发明申请

US20070019058A1 Lithography simulation method, mask pattern preparation method, semiconductor device manufacturing method and recording medium 失效
标题翻译：光刻模拟法，掩模图案制备方法，半导体器件制造方法和记录介质
公开(公告)号：US20070019058A1
公开(公告)日：2007-01-25
申请号：US11485554
申请日：2006-07-13
申请人： Toshiya Kotani , Shigeki Nojima , Shoji Mimotogi
发明人： Toshiya Kotani , Shigeki Nojima , Shoji Mimotogi
IPC分类号： B41J2/385
CPC分类号： G03F7/70433 , G03F7/705
摘要： A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.
摘要翻译：光刻模拟方法包括：获取要在基板上形成的图案的设计数据，并且掩模数据，以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中，根据感兴趣的图案之间的距离，在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置以及相邻区域的图案，所述潜像曲线是构成所述潜像的能量射线的强度分布曲线，所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离，以定义感兴趣的图案的感兴趣的线宽。

9. 发明申请

US20060039596A1 Pattern measuring method, pattern measuring apparatus, photo mask manufacturing method, semiconductor device manufacturing method, and computer program product 审中-公开
标题翻译：图案测量方法，图案测量装置，光掩模制造方法，半导体器件制造方法和计算机程序产品
公开(公告)号：US20060039596A1
公开(公告)日：2006-02-23
申请号：US11205017
申请日：2005-08-17
申请人： Shigeki Nojima , Hiroshi Motoki , Takahiro Ikeda , Satoshi Tanaka , Takeshi Ito
发明人： Shigeki Nojima , Hiroshi Motoki , Takahiro Ikeda , Satoshi Tanaka , Takeshi Ito
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： A pattern measuring method includes preparing a substrate comprising a pattern, extracting a place to be measured on the substrate based on a simulation using pattern data relating to the pattern as input data, generating measurement information for measuring a physical quantity of the place to be measured by a measuring apparatus, and measuring the place to be measured based on the measurement information by the measuring apparatus.
摘要翻译：图案测量方法包括：准备包括图案的基板，基于使用与图案相关的图案数据作为输入数据的模拟，在基板上提取待测量的地方，生成用于测量待测位置的物理量的测量信息通过测量装置，并且基于测量装置的测量信息来测量待测量的位置。

10. 发明申请

US20060033049A1 Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium 失效
公开(公告)号：US20060033049A1
公开(公告)日：2006-02-16
申请号：US11200176
申请日：2005-08-10
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
IPC分类号： G21K5/10
CPC分类号： H01J37/3026 , G03F1/36 , G03F1/68
摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

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