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1. 发明授权

US08630142B2 Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权
标题翻译：半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗
公开(公告)号：US08630142B2
公开(公告)日：2014-01-14
申请号：US13492530
申请日：2012-06-08
申请人： Koji Nii , Shigeki Obayashi , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara
发明人： Koji Nii , Shigeki Obayashi , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译：单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

2. 发明授权

US08487403B2 Semiconductor device 有权
公开(公告)号：US08487403B2
公开(公告)日：2013-07-16
申请号：US12878977
申请日：2010-09-09
申请人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
发明人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

3. 发明申请

US20130049166A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20130049166A1
公开(公告)日：2013-02-28
申请号：US13592949
申请日：2012-08-23
申请人： Toshiaki YONEZU , Takeshi Iwamoto , Shigeki Obayashi , Masashi Arakawa , Kazushi Kono
发明人： Toshiaki YONEZU , Takeshi Iwamoto , Shigeki Obayashi , Masashi Arakawa , Kazushi Kono
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.
摘要翻译：一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。保险丝布线被超过预定值的电流切断。第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中层。在保险丝布线中，在第一通孔布线的外侧形成有一对第二通孔布线，使得第一通孔布线被包围。

4. 发明申请

US20120243302A1 SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE 有权
标题翻译：半导体存储器件，即使在低功耗电压下也能稳定地执行写入和读取，而不会增加电流消耗
公开(公告)号：US20120243302A1
公开(公告)日：2012-09-27
申请号：US13492530
申请日：2012-06-08
申请人： Koji NII , Shigeki OBAYASHI , Hiroshi MAKINO , Koichiro ISHIBASHI , Hirofumi SHINOHARA
发明人： Koji NII , Shigeki OBAYASHI , Hiroshi MAKINO , Koichiro ISHIBASHI , Hirofumi SHINOHARA
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译：单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

5. 发明授权

US08218390B2 Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权
标题翻译：半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗
公开(公告)号：US08218390B2
公开(公告)日：2012-07-10
申请号：US13186769
申请日：2011-07-20
申请人： Koji Nii , Shigeki Obayashi , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara
发明人： Koji Nii , Shigeki Obayashi , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译：单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

6. 发明授权

US08009500B2 Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage 有权
标题翻译：半导体存储器件即使在低电源电压下也能够稳定地执行写入和读取而不增加电流消耗
公开(公告)号：US08009500B2
公开(公告)日：2011-08-30
申请号：US12367871
申请日：2009-02-09
申请人： Koji Nii , Shigeki Obayashi , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara
发明人： Koji Nii , Shigeki Obayashi , Hiroshi Makino , Koichiro Ishibashi , Hirofumi Shinohara
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/063 , G11C11/412
摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
摘要翻译：单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

7. 发明申请

US20100264514A1 SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE 审中-公开
标题翻译：半导体器件和增加电熔丝电阻值的方法
公开(公告)号：US20100264514A1
公开(公告)日：2010-10-21
申请号：US12760648
申请日：2010-04-15
申请人： Takeshi IWAMOTO , Kazushi KONO , Masashi ARAKAWA , Toshiaki YONEZU , Shigeki OBAYASHI
发明人： Takeshi IWAMOTO , Kazushi KONO , Masashi ARAKAWA , Toshiaki YONEZU , Shigeki OBAYASHI
IPC分类号： H01L23/525 , H01L29/86 , H01H85/02
CPC分类号： H01L23/5256 , H01H85/041 , H01L23/5227 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
摘要翻译：提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。电熔丝形成为细层，由主配线和阻挡膜构成。主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

8. 发明授权

US07808076B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07808076B2
公开(公告)日：2010-10-05
申请号：US11958360
申请日：2007-12-17
申请人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
发明人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.
摘要翻译：提供具有小占用面积的电直线状熔断器的半导体器件。多个突出部10f形成在从电熔丝部10a的中间位置偏离的位置，更具体地，形成在远离通孔10e和靠近通孔10d的位置。多个突出部20f形成在从电熔丝部20a的中间位置偏移的位置，更具体地，形成在远离通孔20d和靠近20e的位置。也就是说，突出部分10f和突出部分20f被布置成Z字形。

9. 发明申请

US20100230780A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100230780A1
公开(公告)日：2010-09-16
申请号：US12718593
申请日：2010-03-05
申请人： Shigeki Obayashi
发明人： Shigeki Obayashi
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , G11C17/18 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides a semiconductor device realizing reliable cutting of a fuse without enlarging layout area of a fuse element and the reduced number of wiring layers of a preventing wall that prevents diffusion of fuse copper atoms. A fuse is formed by using a wire in a metal wiring layer as an upper layer in a plurality of metal wiring layers. Wires are disposed just above and just below a fuse each with a gap of at least two wiring layers. In an upper layer, a power wire that transmits power supply voltage is used as a part covering a preventing wall structure just above the fuse.
摘要翻译：本发明提供了一种半导体器件，其实现熔丝的可靠切割，而不会扩大熔丝元件的布局面积，并且减少了阻止熔丝铜原子扩散的防止壁的布线层数。通过在多个金属布线层中的金属布线层中的导线作为上层形成熔丝。电线布置在每个具有至少两个布线层的间隙的保险丝的正上方和正下方。在上层，传输电源电压的电源线被用作覆盖保险丝正上方的预防壁结构的部分。

10. 发明授权

US07745905B2 Semiconductor device and a method of increasing a resistance value of an electric fuse 有权
标题翻译：半导体器件和增加电熔丝电阻值的方法
公开(公告)号：US07745905B2
公开(公告)日：2010-06-29
申请号：US11683053
申请日：2007-03-07
申请人： Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Toshiaki Yonezu , Shigeki Obayashi
发明人： Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Toshiaki Yonezu , Shigeki Obayashi
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01H85/041 , H01L23/5227 , H01L23/525 , H01L23/528 , H01L23/5283 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
摘要翻译：提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。电熔丝形成为细层，由主配线和阻挡膜构成。主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

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