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1. 发明授权

US08890244B2 Lateral power MOSFET structure and method of manufacture 有权
标题翻译：横向功率MOSFET结构及其制造方法
公开(公告)号：US08890244B2
公开(公告)日：2014-11-18
申请号：US12775440
申请日：2010-05-06
申请人： Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1087 , H01L29/42368 , H01L29/66689
摘要： A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor.
摘要翻译：描述具有低比导通电阻的侧向功率MOSFET。铰接圆弧形图案中堆叠的P顶和N级区分离晶体管的源极和漏极。

2. 发明授权

US08749016B2 High voltage MOS device and method for making the same 有权
标题翻译：高压MOS器件及其制造方法
公开(公告)号：US08749016B2
公开(公告)日：2014-06-10
申请号：US12899152
申请日：2010-10-06
申请人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chieh-Chih Chen , Cheng-Chi Lin , Chen-Yuan Lin , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/06
CPC分类号： H01L29/66681 , H01L27/0629 , H01L27/0922 , H01L29/0607 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/7816
摘要： A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.
摘要翻译：高压金属氧化物半导体（HVMOS）器件可以包括源极，漏极，位于源极附近的栅极，基本上设置在漏极与栅极和源极区域之间的漂移区域，以及自屏蔽区域设置在漏极附近。还提供了相应的方法。

3. 发明授权

US08643072B1 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08643072B1
公开(公告)日：2014-02-04
申请号：US13547549
申请日：2012-07-12
申请人： Miao-Chun Chung , An-Li Cheng , Yin-Fu Huang , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Miao-Chun Chung , An-Li Cheng , Yin-Fu Huang , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L29/0619
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括体，栅极，源极，漏极和体接触区域。门是大量的。源极和漏极分别在栅极的相对侧上。体接触区域仅在与源极相邻的部分的区域中。体接触区域电连接到本体。

4. 发明申请

US20130265102A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130265102A1
公开(公告)日：2013-10-10
申请号：US13442340
申请日：2012-04-09
申请人： Chen-Yuan Lin , Cheng-Chi Lin , Ching-Lin Chan , Shih-Chin Lien , Shyi-Yuan Wu
发明人： Chen-Yuan Lin , Cheng-Chi Lin , Ching-Lin Chan , Shih-Chin Lien , Shyi-Yuan Wu
IPC分类号： H01L29/808 , G11C5/14 , H01L21/337
CPC分类号： H01L29/66901 , H01L29/0634 , H01L29/0692 , H01L29/1066 , H01L29/808
摘要： A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type formed in the deep well and extending down from the surface of the substrate; and a second well having the second conductive type formed in the deep well and extending down from the surface of the substrate, and the second well adjacent to the first well. The first well includes a block region and plural finger regions joined to one side of the block region, while the second well includes plural channel regions interlaced with the finger regions to separate the finger regions.
摘要翻译：提供了半导体结构及其制造方法。半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 第一阱具有形成在深阱中并从衬底表面向下延伸的第一导电类型; 以及第二阱，其具有形成在深阱中并从衬底的表面向下延伸的第二导电类型，以及与第一阱相邻的第二阱。第一阱包括连接到块区域的一侧的块区域和多个指状区域，而第二阱包括与手指区域交织的多个沟道区域以分离手指区域。

5. 发明授权

US08421124B2 High-beta bipolar junction transistor and method of manufacture 有权
标题翻译：高β双极结晶体管及其制造方法
公开(公告)号：US08421124B2
公开(公告)日：2013-04-16
申请号：US12723953
申请日：2010-03-15
申请人： Cheng-Chi Lin , Shuo-Lun Tu , Shih-Chin Lien
发明人： Cheng-Chi Lin , Shuo-Lun Tu , Shih-Chin Lien
IPC分类号： H01L31/072
CPC分类号： H01L29/73 , H01L29/0821 , H01L29/66234 , H01L29/66272 , H01L29/7371
摘要： An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.
摘要翻译：公开了一种NPN双极结晶体管，其显示出大于10伏的集电极至发射极击穿电压，并且β大于300.通过用额外的N型层制造晶体管来获得较大的β值，该晶体管减少了复合的复合电子和空穴。

6. 发明授权

US08362558B2 Low on-resistance lateral double-diffused MOS device 有权
标题翻译：低导通电阻横向双扩散MOS器件
公开(公告)号：US08362558B2
公开(公告)日：2013-01-29
申请号：US13100449
申请日：2011-05-04
申请人： Hsueh-I Huang , Chien-Wen Chu , Cheng-Chi Lin , Shih-Chin Lien , Chin-Pen Yeh , Shyi-Yuan Wu
发明人： Hsueh-I Huang , Chien-Wen Chu , Cheng-Chi Lin , Shih-Chin Lien , Chin-Pen Yeh , Shyi-Yuan Wu
IPC分类号： H01L29/02
CPC分类号： H01L29/0847 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.
摘要翻译：提供了横向双扩散MOS器件。该装置包括：具有第一导电类型的第一阱和具有布置在衬底中并且彼此相邻的第二导电类型的第二阱; 漏极和分别设置在第一和第二阱中的具有第一导电类型的源极区域; 设置在源极和漏极区域之间的第一阱上的场氧化物层（FOX）; 设置在延伸到FOX的源极和漏极区域之间的第二阱上的栅极导电层; 在所述基板和所述栅极导电层之间的栅极介电层; 在栅极导电层的一部分下方的第一阱中具有第一导电类型的掺杂区域和连接到漏极区域的FOX。在掺杂区域和源极区域之间的第二阱中限定沟道区域。

7. 发明授权

US08357547B2 Semiconductor bio-sensors and methods of manufacturing the same 有权
标题翻译：半导体生物传感器及其制造方法相同
公开(公告)号：US08357547B2
公开(公告)日：2013-01-22
申请号：US13538455
申请日：2012-06-29
申请人： Ming-Tung Lee , Shih-Chin Lien , Chia-Huan Chang
发明人： Ming-Tung Lee , Shih-Chin Lien , Chia-Huan Chang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： G01N33/525 , G01N27/4145 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
摘要翻译：制造半导体生物传感器的方法包括：提供衬底，在衬底上形成第一介电层，在第一电介质层上形成图案化的第一导电层，图案化的第一导电层包括第一部分和一对第二部分在所述图案化的第一导电层上依次形成第二电介质层，第三电介质层和第四电介质层，在所述第四电介质层中形成空腔，形成通过所述空腔的通孔，暴露所述图案化的第一导电层的第二部分，在所述第四电介质层上形成图案化的第二导电层，在所述图案化的第二导电层上形成钝化层，形成开口，以暴露所述图案化的第一导电层的所述第一部分上的所述第三电介质层的一部分，通过开放。

8. 发明申请

US20120326276A1 Buried Layer of An Integrated Circuit 有权
标题翻译：集成电路的埋层
公开(公告)号：US20120326276A1
公开(公告)日：2012-12-27
申请号：US13596970
申请日：2012-08-28
申请人： Yin-Fu Huang , Ming Rong Chang , Shih-Chin Lien
发明人： Yin-Fu Huang , Ming Rong Chang , Shih-Chin Lien
IPC分类号： H01L29/06
CPC分类号： H01L29/7322 , H01L21/2652 , H01L21/324 , H01L21/761 , H01L29/0821 , H01L29/107 , H01L29/167 , H01L29/66272 , H01L29/78
摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.
摘要翻译：该技术的各个方面都针对集成电路制造方法和集成电路。在一种方法中，通过在半导体材料上通过牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域转移集成电路的半导体材料中的第一电荷型掩埋层植入的第一电荷型掺杂剂。当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏了半导体晶格。之后，生长并除去预退火氧化物。

9. 发明申请

US20120270350A1 SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体生物传感器及其制造方法
公开(公告)号：US20120270350A1
公开(公告)日：2012-10-25
申请号：US13538455
申请日：2012-06-29
申请人： Ming-Tung Lee , Shih-Chin Lien , Chia-Huan Chang
发明人： Ming-Tung Lee , Shih-Chin Lien , Chia-Huan Chang
IPC分类号： H01L21/02
CPC分类号： G01N33/525 , G01N27/4145 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.
摘要翻译：制造半导体生物传感器的方法包括：提供衬底，在衬底上形成第一介电层，在第一电介质层上形成图案化的第一导电层，图案化的第一导电层包括第一部分和一对第二部分在所述图案化的第一导电层上依次形成第二电介质层，第三电介质层和第四电介质层，在所述第四电介质层中形成空腔，通过所述空腔形成通孔，暴露所述图案化的第一导电层的第二部分，在所述第四电介质层上形成图案化的第二导电层，在所述图案化的第二导电层上形成钝化层，形成开口，以暴露所述图案化的第一导电层的所述第一部分上的所述第三电介质层的一部分，通过开放。

10. 发明授权

US08258042B2 Buried layer of an integrated circuit 有权
标题翻译：埋层的集成电路
公开(公告)号：US08258042B2
公开(公告)日：2012-09-04
申请号：US12549869
申请日：2009-08-28
申请人： Yin-Fu Huang , Ming Rong Chang , Shih-Chin Lien
发明人： Yin-Fu Huang , Ming Rong Chang , Shih-Chin Lien
IPC分类号： H01L21/76
CPC分类号： H01L29/7322 , H01L21/2652 , H01L21/324 , H01L21/761 , H01L29/0821 , H01L29/107 , H01L29/167 , H01L29/66272 , H01L29/78
摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.
摘要翻译：该技术的各个方面都针对集成电路制造方法和集成电路。在一种方法中，通过在半导体材料上通过牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域转移集成电路的半导体材料中的第一电荷型掩埋层植入的第一电荷型掺杂剂。当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏半导体晶格。之后，生长并除去预退火氧化物。

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