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1. 发明授权

US09978656B2 Mechanisms for forming fine-pitch copper bump structures 有权
公开(公告)号：US09978656B2
公开(公告)日：2018-05-22
申请号：US13406270
申请日：2012-02-27
申请人： Tsung-Shu Lin , Han-Ping Pu , Ming-Da Cheng , Chang-Chia Huang , Hao-Juin Liu
发明人： Tsung-Shu Lin , Han-Ping Pu , Ming-Da Cheng , Chang-Chia Huang , Hao-Juin Liu
IPC分类号： H01L23/00 , H01L23/29 , H01L23/31 , H01L21/56
CPC分类号： H01L23/293 , H01L21/568 , H01L23/3157 , H01L24/02 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05541 , H01L2224/05572 , H01L2224/05647 , H01L2224/10126 , H01L2224/1146 , H01L2224/1147 , H01L2224/1181 , H01L2224/1191 , H01L2224/13005 , H01L2224/13007 , H01L2224/13022 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13164 , H01L2224/16237 , H01L2224/73104 , H01L2224/81193 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/206 , H01L2924/207 , H01L2924/01082 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

2. 发明授权

US09887144B2 Ring structure for chip packaging 有权
公开(公告)号：US09887144B2
公开(公告)日：2018-02-06
申请号：US13227983
申请日：2011-09-08
申请人： Wen-Yi Lin , Yu-Chih Liu , Ming-Chih Yew , Tsung-Shu Lin , Bor-Rung Su , Jing Ruei Lu , Wei-Ting Lin
发明人： Wen-Yi Lin , Yu-Chih Liu , Ming-Chih Yew , Tsung-Shu Lin , Bor-Rung Su , Jing Ruei Lu , Wei-Ting Lin
IPC分类号： H01L23/10 , H01L23/16 , H01L23/36 , H01L21/56 , H01L23/00
CPC分类号： H01L23/10 , H01L21/563 , H01L23/16 , H01L23/36 , H01L24/16 , H01L24/32 , H01L24/33 , H01L2224/131 , H01L2224/16225 , H01L2224/29099 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

3. 发明授权

US09548283B2 Package redistribution layer structure and method of forming same 有权
标题翻译：包装再分配层结构及其形成方法
公开(公告)号：US09548283B2
公开(公告)日：2017-01-17
申请号：US13542528
申请日：2012-07-05
申请人： Tsung-Shu Lin , Hung-Jui Kuo , Yi-Wen Wu
发明人： Tsung-Shu Lin , Hung-Jui Kuo , Yi-Wen Wu
IPC分类号： H01L29/49 , H01L23/00 , H01L23/538 , H01L25/10 , H01L23/31 , H01L25/16
CPC分类号： H01L24/73 , H01L23/3121 , H01L23/5389 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/107 , H01L2924/0002 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.
摘要翻译：封装封装（PoP）器件包括在衬底上的底部封装和耦合底部封装和衬底的第一组导电元件。 PoP器件还包括在底部封装上的顶部封装以及将顶部封装耦合到衬底的再分配层。形成PoP器件的方法包括将第一封装耦合到衬底; 以及在所述第一封装和所述衬底的顶表面上形成再分布层。该方法还包括将第二包装物耦合到再分配层，其中再分配层将第二包装物耦合到基底。

4. 发明授权

US09214192B2 Digital video processing and storage system for video, audio and ancillary data 有权
标题翻译：用于视频，音频和辅助数据的数字视频处理和存储系统
公开(公告)号：US09214192B2
公开(公告)日：2015-12-15
申请号：US11495255
申请日：2006-07-28
申请人： Shu Lin , Donald Henry Willis , Mark Alan Schultz
发明人： Shu Lin , Donald Henry Willis , Mark Alan Schultz
IPC分类号： H04N9/80 , G11B27/30 , G11B27/034 , G11B27/32 , G11B27/34 , G11B27/36
CPC分类号： G11B27/3027 , G11B27/034 , G11B27/309 , G11B27/329 , G11B27/34 , G11B27/36 , G11B2220/213 , G11B2220/216 , G11B2220/2562
摘要： A video processing system adaptively generates and processes volume/file structure and navigation data of different data format and converts data between different formats for decoding, recording and other applications. The system processes the volume/file structure and navigation data in distinct modes including (a) pre-processing, (b) contemporaneous and (c) post-processing modes. In addition, the system provides navigation information supporting navigation through different images of one or more video programs by parsing encoded packetized data representative of a sequence of individual images to determine parameters to support navigation through the sequence of individual images. The determined parameters are formatted into a predetermined data structure and incorporated into a pre-formed navigation data field.
摘要翻译：视频处理系统自适应地生成和处理不同数据格式的音量/文件结构和导航数据，并且在不同格式之间转换数据以进行解码，记录和其他应用。系统以不同的模式处理音量/文件结构和导航数据，包括（a）预处理，（b）同时期和（c）后处理模式。此外，该系统提供导航信息，以支持通过一个或多个视频节目的不同图像导航，通过解析表示单个图像序列的编码分组化数据来确定参数以支持通过单独图像序列的导航。所确定的参数被格式化为预定的数据结构，并且被合并到预先形成的导航数据字段中。

5. 发明申请

US20150090139A1 COLLINEAR PRINTING METHOD WITH ROLLER-TYPE UPFRONT GOLD-STAMPING, MATTING AND SNOWFLAKE PRINTED PATTERNS, AND PRINTED PRODUCT THEREOF 审中-公开
标题翻译：具有滚筒式上光金烫印，花纹和雪花印花图案的圆柱印刷方法及其印刷产品
公开(公告)号：US20150090139A1
公开(公告)日：2015-04-02
申请号：US14042678
申请日：2013-09-30
申请人： YAN-SHU LIN
发明人： YAN-SHU LIN
IPC分类号： B44C1/24
CPC分类号： B44C1/24 , B41F16/0013 , B41F16/0033 , B41M1/14
摘要： Disclosed is a collinear printing method with roller-type upfront gold-stamping, matting and snowflake printed patterns and a printed product manufactured by the method. In a roller-type seven-color automatic printing machine, an adhesive glue is filled into a first printing ink set, and a second printing ink set is modified to be a cold stamping device and mounted with a drum-shaped foil, and the middle section of each printing ink set is filled with printing inks of different desired colors, and the last printing ink set is filled with a repulsive paint and a gold paint. In a printing manufacturing process, a printed matter is processed by a partial cold stamping operation, each of the expected color printing operations is completed in a same-line procedure, the last printing ink set coats the repulsive paint and the gold paint onto the printed matter, and a ground or snowflake pattern is printed onto the printed matter in the same-line according to the mesh size of a mesh ink roller of the gold paint.
摘要翻译：公开了一种具有辊式前期金印，消光和雪花印刷图案的共线印刷方法以及通过该方法制造的印刷产品。在辊式七色自动印刷机中，将胶粘剂填充到第一印刷油墨组中，并且将第二印刷油墨组改性为冷冲压装置并安装有鼓形箔，并且中间每个印刷油墨组的部分填充有不同所需颜色的印刷油墨，并且最后一个印刷油墨组填充有排斥油漆和金漆。在印刷制造过程中，通过部分冷冲压操作处理印刷品，预期的彩色印刷操作以相同的程序完成，最后的印刷油墨组将排斥涂料和金漆涂覆到印刷物质，并且根据金漆的网眼油墨辊的网格尺寸，在同一行上将印刷物或地面或雪花图案印刷到印刷品上。

6. 发明授权

US08976529B2 Lid design for reliability enhancement in flip chip package 有权
标题翻译：封装设计，用于倒装芯片封装的可靠性提升
公开(公告)号：US08976529B2
公开(公告)日：2015-03-10
申请号：US13007249
申请日：2011-01-14
申请人： Wen-Yi Lin , Po-Yao Lin , Tsung-Shu Lin , Kuo-Chin Chang , Shou-Yi Wang
发明人： Wen-Yi Lin , Po-Yao Lin , Tsung-Shu Lin , Kuo-Chin Chang , Shou-Yi Wang
IPC分类号： H05K7/20 , H01L23/16 , H01L23/055 , H01L23/00
CPC分类号： H01L23/16 , H01L23/055 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
摘要： In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.
摘要翻译：在包装结构中，加强环在第一包装部件的顶表面上结合并结合。第二包装部件在第一包装部件的顶部表面上结合并且被加强环环绕。金属盖已经结合到加强环上。金属盖具有通孔。

7. 发明申请

US20130256874A1 Elongated Bumps in Integrated Circuit Devices 有权
标题翻译：集成电路器件中的伸长的冲击波
公开(公告)号：US20130256874A1
公开(公告)日：2013-10-03
申请号：US13559840
申请日：2012-07-27
申请人： Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
发明人： Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
IPC分类号： H01L23/498
CPC分类号： H01L23/3192 , H01L23/293 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05005 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/13012 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012 , H01L2924/206 , H01L2924/01047
摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.
摘要翻译：一种器件包括衬底，衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。钝化层具有与金属焊盘重叠的第一开口，其中第一开口具有在平行于衬底的主表面的方向上测量的第一横向尺寸。聚合物层在钝化层上方并覆盖金属焊盘的边缘部分。聚合物层具有与金属垫重叠的第二开口。第二开口具有在该方向上测量的第二横向尺寸。第一横向尺寸大于第二横向尺寸大于约7μm。下冲击冶金（UBM）包括第二开口中的第一部分和覆盖聚合物层部分的第二部分。

8. 发明授权

US08486790B2 Manufacturing method for metal gate 有权
标题翻译：金属门制造方法
公开(公告)号：US08486790B2
公开(公告)日：2013-07-16
申请号：US13184572
申请日：2011-07-18
申请人： Po-Cheng Huang , Kuo-Chih Lai , Ching-I Li , Yu-Shu Lin , Ya-Jyuan Hung , Yen-Liang Lu , Yu-Wen Wang , Hsin-Chih Yu
发明人： Po-Cheng Huang , Kuo-Chih Lai , Ching-I Li , Yu-Shu Lin , Ya-Jyuan Hung , Yen-Liang Lu , Yu-Wen Wang , Hsin-Chih Yu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/4966 , H01L29/51 , H01L29/6659 , H01L29/66606 , H01L29/7833
摘要： A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.
摘要翻译：金属栅极的制造方法包括提供具有形成在其上的电介质层和多晶硅层的基板，多晶硅层，在多晶硅层上形成保护层，在保护层上形成图案化的硬掩模，进行第一蚀刻工艺蚀刻保护层和多晶硅层，以在衬底上形成具有第一高度的虚拟栅极，形成覆盖图案化硬掩模和伪栅极的多层介电结构，去除伪栅极以在衬底上形成栅极沟槽，以及在所述栅极沟槽中形成具有第二高度的金属栅极。金属栅极的第二高度基本上等于虚拟栅极的第一高度。

9. 发明授权

US08444793B2 Semiconductor device and fabricating method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08444793B2
公开(公告)日：2013-05-21
申请号：US12701615
申请日：2010-02-08
申请人： Hsin-Chang Hsiung , Shu-Lin Ho
发明人： Hsin-Chang Hsiung , Shu-Lin Ho
IPC分类号： B29C73/04 , B29C65/54 , B29C63/22 , B32B37/06 , B32B37/12 , B32B38/10 , B32B43/00 , C08J5/12
CPC分类号： B32B38/1841 , B32B37/1284 , B32B2037/268 , B32B2307/542 , B32B2309/105 , B32B2457/14 , Y10T156/11 , Y10T156/1153 , Y10T428/31515
摘要： The present invention provides a semiconductor device and a fabricating method thereof. The fabricating method comprises: providing a first substrate; forming a soft dry film having an adhesive film and a release film; sticking the soft dry film on the first substrate with the adhesive film; removing the release film; sticking a second substrate on the adhesive film; and heating the adhesive film to solidify the adhesive film to form a solid adhesive film. The semiconductor device comprises: a first substrate, a solid adhesive film, and a second substrate. The solid adhesive film is formed on the first substrate, and the second substrate is formed on the solid adhesive film.
摘要翻译：本发明提供一种半导体器件及其制造方法。制造方法包括：提供第一基板; 形成具有粘合膜和脱模膜的软干膜; 用粘合膜将柔软干膜粘在第一基片上; 去除脱模膜; 在粘合膜上粘贴第二衬底; 并加热粘合剂膜以固化粘合剂膜以形成固体粘合剂膜。半导体器件包括：第一衬底，固体粘合膜和第二衬底。固体粘合膜形成在第一基板上，第二基板形成在固体粘合膜上。

10. 发明申请

US20120217632A1 Extending Metal Traces in Bump-on-Trace Structures 有权
标题翻译：在轨迹结构中扩展金属轨迹
公开(公告)号：US20120217632A1
公开(公告)日：2012-08-30
申请号：US13035586
申请日：2011-02-25
申请人： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
发明人： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
IPC分类号： H01L23/498
CPC分类号： H01L24/16 , H01L23/49816 , H01L23/49838 , H01L24/13 , H01L24/17 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16013 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
摘要翻译：一种装置包括工件和工件表面上的金属迹线。在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

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