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1. 发明授权

US09007830B2 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US09007830B2
公开(公告)日：2015-04-14
申请号：US13960140
申请日：2013-08-06
申请人： Solid State Storage Solutions, Inc.
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34 , G11C29/00 , G11C16/34
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.
摘要翻译：一种非易失性存储装置，包括：控制单元，具有可再充电的非易失性存储器的主存储介质，其适用于即使存在故障存储单元时也可操作;以及存储区域，存储包含故障存储单元的主存储介质的故障区域的登记地址值记忆细胞存储在电可重新加载的非易失性存储器中的数据被划分为块，每个块具有要管理的多个数据，并且由控制单元分配有访问地址。在每个块中提供管理信息区域。控制单元执行主存储介质的访问请求和主存储介质的各个存储单元的重新加载的故障区域的管理和重新加载的次数。

2. 发明申请

US20140185380A1 SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 有权
标题翻译：具有故障细胞的半导体存储器件
公开(公告)号：US20140185380A1
公开(公告)日：2014-07-03
申请号：US13960140
申请日：2013-08-06
申请人： Solid State Storage Solutions, Inc.
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi INOUE , Shigemasa SHIOTA , Masashi NAITO
IPC分类号： G11C16/34 , G11C29/00
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

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