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1. 发明申请

US20120140565A1 Scalable Electrically Eraseable And Programmable Memory 有权
标题翻译：可扩展电擦除和可编程存储器
公开(公告)号：US20120140565A1
公开(公告)日：2012-06-07
申请号：US13365216
申请日：2012-02-02
申请人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
IPC分类号： G11C16/04
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/82385 , H01L21/823857 , H01L27/105 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/7881
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括连接到第一位线的第一非易失性存储器晶体管，连接到第二位线的第二非易失性存储晶体管和耦合到公共源极线的源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一扩散区域和与第二非易失性存储晶体管的源极区域连续的第二扩散区域。

2. 发明授权

US08093650B2 Scalable electrically eraseable and programmable memory (EEPROM) cell array 有权
标题翻译：可扩展的电可擦除和可编程存储器（EEPROM）单元阵列
公开(公告)号：US08093650B2
公开(公告)日：2012-01-10
申请号：US12366569
申请日：2009-02-05
申请人： Sorin S. Georgescu , A. Peter Cosmin
发明人： Sorin S. Georgescu , A. Peter Cosmin
IPC分类号： H01L27/115
CPC分类号： H01L29/7883 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
摘要翻译：非易失性存储器（NVM）系统包括以双阱结构制造的多个NVM单元。每个NVM单元包括存取晶体管和NVM晶体管，其中存取晶体管具有与NVM晶体管的源极区域连续的漏极区域。阵列列中的每个NVM晶体管的漏极区域共同连接到相应的位线。阵列的一行中的每个NVM晶体管的控制栅极通常连接到相应的字线。阵列中每个存取晶体管的源极区域通常耦合。 NVM单元被编程和擦除，而不必在存取晶体管的栅极电介质层上施加高编程电压VPP。因此，NVM电池可以缩小到0.35微米以下的几何尺寸。

3. 发明授权

US07558111B2 Non-volatile memory cell in standard CMOS process 有权
标题翻译：标准CMOS工艺中的非易失性存储单元
公开(公告)号：US07558111B2
公开(公告)日：2009-07-07
申请号：US11469840
申请日：2006-09-01
申请人： Sabin A. Eftimie , Ilie Marian I. Poenaru , Sorin S. Georgescu
发明人： Sabin A. Eftimie , Ilie Marian I. Poenaru , Sorin S. Georgescu
IPC分类号： G11C14/00
CPC分类号： G11C16/0441
摘要： A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
摘要翻译：一种用常规CMOS工艺制造的非易失性存储单元，包括具有NMOS晶体管的触发器电路，该NMOS晶体管与写入PMOS电容器和擦除PMOS电容器共享浮置栅极。通过将Fowler-Nordheim隧道穿过擦除PMOS电容器来实现擦除功能，从而在浮动栅极上提供正电荷。通过引入通过NMOS晶体管的Fowler-Nordheim隧道实现写入功能，从而在浮动栅极上提供负电荷。写入PMOS电容器在擦除和写入操作期间提供偏置电压。在读操作之前，触发器电路被复位。如果浮置栅极存储正电荷，则NMOS晶体管导通，从而切换触发器电路的状态。如果浮动栅极存储负电荷，则NMOS晶体管截止，从而使触发器电路处于复位状态。

4. 发明授权

US07547944B2 Scalable electrically eraseable and programmable memory (EEPROM) cell array 有权
标题翻译：可扩展的电可擦除和可编程存储器（EEPROM）单元阵列
公开(公告)号：US07547944B2
公开(公告)日：2009-06-16
申请号：US11278103
申请日：2006-03-30
申请人： Sorin S. Georgescu , Adam P. Cosmin
发明人： Sorin S. Georgescu , Adam P. Cosmin
IPC分类号： H01L27/115
CPC分类号： H01L29/7883 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
摘要翻译：非易失性存储器（NVM）系统包括以双阱结构制造的多个NVM单元。每个NVM单元包括存取晶体管和NVM晶体管，其中存取晶体管具有与NVM晶体管的源极区域连续的漏极区域。阵列列中的每个NVM晶体管的漏极区域共同连接到相应的位线。阵列的一行中的每个NVM晶体管的控制栅极通常连接到相应的字线。阵列中每个存取晶体管的源极区域通常耦合。 NVM单元被编程和擦除，而不必在存取晶体管的栅极电介质层上施加高编程电压VPP。因此，NVM电池可以缩小到0.35微米以下的几何尺寸。

5. 发明授权

US07236046B2 LED bias current control using adaptive fractional charge pump 有权
$LED bias current control using adaptive fractional charge pump$
标题翻译： LED偏置电流控制采用自适应分数电荷泵
公开(公告)号：US07236046B2
公开(公告)日：2007-06-26
申请号：US11264884
申请日：2005-11-01
申请人： Sorin S. Georgescu , Anthony G. Russell , Chris B. Bartholomeusz
发明人： Sorin S. Georgescu , Anthony G. Russell , Chris B. Bartholomeusz
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H05B33/0815 , Y02B20/347
摘要： A charge pump provides a multiplication factor of 4/3 by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the voltage potential across the first capacitor is added to the input voltage to generate the output voltage. In a third mode, the voltage potential across the first capacitor is subtracted from the sum of the input voltage and the voltage potential across the second capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired 4/3× voltage multiplication. This relatively low multiplication factor can be beneficial in applications such as white LED driver circuits, particularly where the input voltage is provided by a battery.
摘要翻译：电荷泵通过使用三相工作模式提供4/3的倍增系数。在第一模式中，第一和第二电容器从输入电压充电，而第三电容器基于第三电容器中存储的电荷来驱动输出电压。在第二模式中，将第一电容器两端的电位电压加到输入电压上以产生输出电压。在第三模式中，从第二电容器两端的输入电压和电压电位之和减去第一电容器两端的电压，以产生输出电压。以这种方式操作，第一，第二和第三电容器将提供期望的4 / 3x电压倍增。这种相对较低的乘法因子在诸如白色LED驱动器电路的应用中是有益的，特别是在电池提供输入电压的情况下。

6. 发明授权

US08750041B2 Scalable electrically erasable and programmable memory 有权
标题翻译：可扩展的电可擦除和可编程存储器
公开(公告)号：US08750041B2
公开(公告)日：2014-06-10
申请号：US13365216
申请日：2012-02-02
申请人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
IPC分类号： G11C16/04 , H01L29/788 , H01L27/115
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/82385 , H01L21/823857 , H01L27/105 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/7881
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括连接到第一位线的第一非易失性存储器晶体管，连接到第二位线的第二非易失性存储晶体管和耦合到公共源极线的源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一扩散区域和与第二非易失性存储晶体管的源极区域连续的第二扩散区域。

7. 发明授权

US07602232B2 Programmable fractional charge pump for DC-DC converter 有权
$Programmable fractional charge pump for DC-DC converter$
标题翻译：用于DC-DC转换器的可编程分数电荷泵
公开(公告)号：US07602232B2
公开(公告)日：2009-10-13
申请号：US11746588
申请日：2007-05-09
申请人： Sorin S. Georgescu , Anthony G. Russell , Chris B. Bartholomeusz
发明人： Sorin S. Georgescu , Anthony G. Russell , Chris B. Bartholomeusz
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H02M2003/072
摘要： A charge pump provides a programmable multiplication factor for generating an output voltage. A first output voltage may be generated by connecting a first plurality of N capacitors in a first plurality of (N+1) configurations. A second output voltage may be generated by connecting a second plurality of M capacitors in a second plurality of M+1 configurations. The first plurality of N capacitors and the second plurality of M capacitors have one or more capacitors in common. The integers M and N may be equal, although this is not required. The first plurality of configurations is different than the second plurality of configurations, thereby providing different multiplication factors for the first and second pluralities of configurations. In one embodiment, the first plurality of (N+1) configurations results in an output voltage of about 3/4× an input voltage.
摘要翻译：电荷泵提供用于产生输出电压的可编程乘法因子。可以通过以第一多个（N + 1）配置连接第一多个N个电容器来产生第一输出电压。可以通过以第二多个M + 1配置的第二多个M个电容器连接来产生第二输出电压。第一多个N个电容器和第二个多个M个电容器具有共同的一个或多个电容器。整数M和N可以相等，尽管这不是必需的。第一多个配置与第二多个配置不同，从而为第一和第二多个配置提供不同的乘法因子。在一个实施例中，第一多个（N + 1）配置导致输入电压约为3 / 4x的输出电压。

8. 发明授权

US07557641B2 Fractional charge pump for step-down DC-DC converter 有权
标题翻译：降压式DC-DC转换器的分数电荷泵
公开(公告)号：US07557641B2
公开(公告)日：2009-07-07
申请号：US11678048
申请日：2007-02-22
申请人： Sorin S. Georgescu , Anthony G. Russell , Chris B. Bartholomeusz
发明人： Sorin S. Georgescu , Anthony G. Russell , Chris B. Bartholomeusz
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H02M2003/072
摘要： A charge pump provides a multiplication factor of ⅔ by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capacitor. In a second mode, the output terminal is connected to the common node of the first and second capacitors. In a third mode, the voltage potential across the second capacitor is subtracted from the sum of the input voltage and the voltage potential across the first capacitor to generate the output voltage. Operated in this manner, the first, second, and third capacitors will provide the desired ⅔× voltage multiplication. This relatively low multiplication factor can be beneficial in applications requiring 2.5V and 1.8V supplies for integrated circuits, particularly where the input voltage is provided by a lithium battery.
摘要翻译：电荷泵通过使用三相工作模式提供2/3的倍增系数。在第一模式中，第一和第二电容器从输入电压充电，而第三电容器基于第三电容器中存储的电荷来驱动输出电压。在第二模式中，输出端子连接到第一和第二电容器的公共节点。在第三模式中，从第一电容器两端的输入电压和电压电平之和减去第二电容器两端的电压电位，以产生输出电压。以这种方式操作，第一，第二和第三电容器将提供期望的2 / 3x电压倍增。这种相对较低的乘法因子对于集成电路需要2.5V和1.8V电源的应用可能是有益的，特别是在输入电压由锂电池提供的情况下。

9. 发明授权

US07528436B2 Scalable electrically eraseable and programmable memory 有权
标题翻译：可扩展的电可擦除和可编程存储器
公开(公告)号：US07528436B2
公开(公告)日：2009-05-05
申请号：US11470245
申请日：2006-09-05
申请人： Sorin S. Georgescu , Adam Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , Adam Peter Cosmin , George Smarandoiu
IPC分类号： H01L29/76
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储晶体管，第二非易失性存储晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储晶体管的源极区域连续的第二源极区域和向下延伸穿过第一阱区域以接触第二阱区域的漏极区域。第一，第二和第三半导体区域和第二阱区域具有第一导电类型，并且第一阱区域具有与第一导电类型相反的第二导电类型。

10. 发明申请

US20080130362A1 Method For Reducing Charge Loss In Analog Floating Gate Cell 有权
标题翻译：减少模拟浮动栅极电荷损失的方法
公开(公告)号：US20080130362A1
公开(公告)日：2008-06-05
申请号：US11943578
申请日：2007-11-20
申请人： Radu A. Sporea , Sorin S. Georgescu , Ilie Marian I. Poenaru
发明人： Radu A. Sporea , Sorin S. Georgescu , Ilie Marian I. Poenaru
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.
摘要翻译：电压参考电路响应于第一非易失性存储器（NVM）晶体管的编程阈值电压提供参考电压。通过将编程电压施加到隧道电容器的公共连接的源极/漏极区域来编程第一NVM晶体管的阈值电压，隧道电容器与第一NVM晶体管共享浮置栅极。在电压参考电路的正常工作期间，隧道电容器的源/漏区连接到具有与第一NVM晶体管的浮置栅极相同的电和热特性的第二NVM晶体管。结果，有利地最小化了来自第一NVM晶体管的浮置栅极的电荷损耗。

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