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1. 发明授权

US08397090B2 Operating integrated circuit logic blocks at independent voltages with single voltage supply 有权
标题翻译：使用单电源供电的独立电压下工作的集成电路逻辑块
公开(公告)号：US08397090B2
公开(公告)日：2013-03-12
申请号：US11636425
申请日：2006-12-08
申请人： Stephen H. Gunther , Edward Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Mike Cornaby
发明人： Stephen H. Gunther , Edward Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Mike Cornaby
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.
摘要翻译：描述以独立电压操作集成电路（IC）的各种逻辑块的方法和装置。在一个实施例中，基于对相应域的组件的功率消耗进行修改的指示来调整对IC中的一个或多个域的功率供给。还描述了其它实施例。

2. 发明授权

US07454596B2 Method and apparatus for partitioned pipelined fetching of multiple execution threads 失效
公开(公告)号：US07454596B2
公开(公告)日：2008-11-18
申请号：US11479345
申请日：2006-06-29
申请人： Stephan Jourdan , Robert Hinton
发明人： Stephan Jourdan , Robert Hinton
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storage in a branch prediction output queue is pre-allocated to a portion of the thread in one branch prediction stage in order to prevent stalling of subsequent stages in the branch prediction pipeline. In another embodiment, an instruction fetch stage fetches instructions at a fetch address corresponding to a portion of the selected thread. Another instruction fetch stage stores the instruction data in an instruction fetch output queue if enough storage is available. Otherwise, instruction fetch stages corresponding to the selected thread are invalidated and refetched to avoid stalling preceding stages in the instruction fetch pipeline, which may be fetching instructions of another thread.

3. 发明申请

US20080104425A1 INDEPENDENT POWER CONTROL OF PROCESSING CORES 有权
标题翻译：加工过程中的独立功率控制
公开(公告)号：US20080104425A1
公开(公告)日：2008-05-01
申请号：US11555609
申请日：2006-11-01
申请人： Stephen H. Gunther , Edward A. Burton , Stephen H. Gunther , Robert Greiner , Michael Cornaby , Anant Deval , Stephan Jourdan
发明人： Stephen H. Gunther , Edward A. Burton , Stephen H. Gunther , Robert Greiner , Michael Cornaby , Anant Deval , Stephan Jourdan
IPC分类号： G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores
摘要翻译：两个或多个处理核心的独立功率控制。更具体地，本发明的至少一个实施例涉及一种将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术

4. 发明申请

US20080059779A1 Overriding a static prediction 有权
标题翻译：覆盖静态预测
公开(公告)号：US20080059779A1
公开(公告)日：2008-03-06
申请号：US11513709
申请日：2006-08-31
申请人： Mark C. Davis , Stephan Jourdan , Robert L. Hinton , Boyd S. Phelps
发明人： Mark C. Davis , Stephan Jourdan , Robert L. Hinton , Boyd S. Phelps
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3846 , G06F9/3848
摘要： In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定对应于预测地址的条目是否存在于第一预测器中的方法，以及如果该条目存在于第一预测器中则覆盖与预测地址对应的第二预测器的预测输出。描述和要求保护其他实施例。

5. 发明授权

US07181597B2 Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module 失效
标题翻译：解码指令，用于跟踪缓存恢复状态，系统将解码的操作传递到跟踪缓存和执行分配模块
公开(公告)号：US07181597B2
公开(公告)日：2007-02-20
申请号：US11217707
申请日：2005-08-31
申请人： John Alan Miller , Stephan Jourdan
发明人： John Alan Miller , Stephan Jourdan
IPC分类号： G06F9/06
CPC分类号： G06F9/3808 , G06F9/3824 , G06F9/3826
摘要： A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.
摘要翻译：管理处理器指令的系统和方法提供增强的性能。该系统和方法提供用解码器将第一指令解码为多个操作。操作的第一个副本从解码器传递到与跟踪缓存相关联的构建引擎。该系统和方法进一步提供将操作的第二副本从解码器直接传递到后端分配模块，使得操作绕过构建引擎并且分配模块处于解码器读取状态。

6. 发明申请

US20070005940A1 System, apparatus and method of executing a micro operation 审中-公开
标题翻译：执行微操作的系统，装置和方法
公开(公告)号：US20070005940A1
公开(公告)日：2007-01-04
申请号：US11170076
申请日：2005-06-30
申请人： Zeev Sperber , Guillermo Savransky , Sagi Lahav , Thierry Pons , Stephan Jourdan
发明人： Zeev Sperber , Guillermo Savransky , Sagi Lahav , Thierry Pons , Stephan Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3824 , G06F9/3832
摘要： Embodiments of the present invention provide an apparatus, system, and method of routing a source operand. Some demonstrative embodiments my include replacing a source operand of a micro operation to be executed by an execution unit with a value type representing a source value, e.g., if the source operand corresponds to the source value. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种用于路由源操作数的装置，系统和方法。一些说明性实施例，我的包括用代表源值的值类型替换由执行单元执行的微操作的源操作数，例如，如果源操作数对应于源值。描述和要求保护其他实施例。

7. 发明申请

US20060123219A1 Intra-instruction fusion 审中-公开
标题翻译：指令内融合
公开(公告)号：US20060123219A1
公开(公告)日：2006-06-08
申请号：US11339019
申请日：2006-01-24
申请人： Nicholas Samra , Stephan Jourdan
发明人： Nicholas Samra , Stephan Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/3853
摘要： Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.
摘要翻译：将微操作（uops）融合在一起。内部指令融合可以在微处理器内提高高速缓冲存储器存储效率和计算机指令处理带宽，而不会导致重大的计算机系统成本。 Uops被融合，存储在缓存中，未融合，并行执行并退出，以优化成本和性能。

8. 发明申请

US20050193278A1 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor 有权
标题翻译：从处理器中同时处理的物理线程的数量解耦逻辑线程数
公开(公告)号：US20050193278A1
公开(公告)日：2005-09-01
申请号：US10745527
申请日：2003-12-29
申请人： Per Hammarlund , Stephan Jourdan , Pierre Michaud , Alexandre Farcy , Morris Marden , Robert Hinton , Douglas Carmean
发明人： Per Hammarlund , Stephan Jourdan , Pierre Michaud , Alexandre Farcy , Morris Marden , Robert Hinton , Douglas Carmean
IPC分类号： G06F9/48 , G06F11/00
CPC分类号： G06F9/485 , G06F9/3851
摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
摘要翻译：管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

9. 发明申请

US20050149709A1 Prediction based indexed trace cache 审中-公开
标题翻译：基于预测的索引跟踪缓存
公开(公告)号：US20050149709A1
公开(公告)日：2005-07-07
申请号：US10748285
申请日：2003-12-29
申请人： Stephan Jourdan
发明人： Stephan Jourdan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3808
摘要： A system and method for compensating for branching instructions in trace caches is disclosed. A branch predictor uses the branching behavior of previous branching instructions to select between several traces beginning at the same linear instruction pointer (LIP) or instruction. The fetching mechanism of the processor selects the trace that most closely matches the previous branching behavior. In one embodiment, a new trace is generated only if a divergence occurs within a predetermined location. A divergence is a branch that is recorded as following one path (i.e. taken) and during execution follows a different path (i.e. not taken).
摘要翻译：公开了用于补偿跟踪高速缓存中的分支指令的系统和方法。分支预测器使用先前分支指令的分支行为来选择在相同的线性指令指针（LIP）或指令开始的多个跟踪之间。处理器的提取机制选择与前一个分支行为最匹配的跟踪。在一个实施例中，仅当在预定位置内发生发散时才产生新迹线。分歧是一个分支，被记录为如下一个路径（即采取），并且在执行期间遵循不同的路径（即不采取）。

10. 发明申请

US20050138295A1 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US20050138295A1
公开(公告)日：2005-06-23
申请号：US10743134
申请日：2003-12-23
申请人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出，则重置状态位。

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