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1. 发明授权

US07539968B2 Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints 失效
标题翻译：集成电路设计的迭代合成，用于实现电源关闭，同时保持现有的设计约束
公开(公告)号：US07539968B2
公开(公告)日：2009-05-26
申请号：US11759332
申请日：2007-06-07
申请人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译：描述了迭代地合成集成电路设计以获得功率闭合的方法。在一个实施例中，集成电路设计最初被合成以满足定时和功率约束。将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。

2. 发明授权

US07886253B2 Design structure for performing iterative synthesis of an integrated circuit design to attain power closure 有权
标题翻译：用于执行集成电路设计的迭代合成以实现功率闭合的设计结构
公开(公告)号：US07886253B2
公开(公告)日：2011-02-08
申请号：US11872731
申请日：2007-10-16
申请人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译：描述了执行集成电路设计的迭代合成以实现功率闭合的设计结构。在一个实施例中，设计结构体现在计算机可读介质中，并具有初始合成集成电路设计以满足定时和功率约束的能力。将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。

3. 发明授权

US07873923B2 Power gating logic cones 有权
标题翻译：电源门控逻辑锥
公开(公告)号：US07873923B2
公开(公告)日：2011-01-18
申请号：US12038845
申请日：2008-02-28
申请人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F2217/78
摘要： Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.
摘要翻译：描述了电源门控逻辑锥。在一个实施例中，一种方法包括用于集成电路（IC）设计的合成逻辑; 识别切换小于阈值的逻辑内的低交换节点; 基于所识别的低交换节点确定潜在功率门控锥（PGC）; 确定潜在PGC的功率选通逻辑表达式，其包括对最不切换的电位PGC的最小输入集合; 确定使用电源门控逻辑表达式的节能是否符合标准; 并接受潜在的PGC以满足标准。

4. 发明申请

US20090100398A1 STRUCTURE FOR PERFORMING ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN TO ATTAIN POWER CLOSURE 有权
标题翻译：用于执行集成电路设计的迭代合成以实现电源闭合的结构
公开(公告)号：US20090100398A1
公开(公告)日：2009-04-16
申请号：US11872731
申请日：2007-10-16
申请人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译：描述了执行集成电路设计的迭代合成以实现功率闭合的设计结构。在一个实施例中，设计结构体现在计算机可读介质中，并具有初始合成集成电路设计以满足定时和功率约束的能力。将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。

5. 发明申请

US20080005712A1 METHOD OF OPTIMIZING CUSTOMIZABLE FILLER CELLS IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN PROCESS 有权
标题翻译：在一体化电路设计过程中优化可定制填充电池的方法
公开(公告)号：US20080005712A1
公开(公告)日：2008-01-03
申请号：US11427719
申请日：2006-06-29
申请人： Steven E. Charlebois , Paul E. Dunn , George W. Rohrbaugh
发明人： Steven E. Charlebois , Paul E. Dunn , George W. Rohrbaugh
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.
摘要翻译：一种用于在集成电路物理设计过程中优化可定制填充单元的系统和方法。特别地，本公开的填充单元布置算法用于在电路布局中优化可定制填充单元的方法中。填充单元布置算法执行在给定电路布局内选择起始点的操作，选择调整逻辑单元的位置的方向，调整逻辑单元的位置，从而组合填充单元以增加累积面积当形成可定制的填充单元时暂停调节操作; 并从新形成的可定制填充单元的点恢复调整操作。另外，提供了通过使用填充单元布置算法来优化集成电路设计中的可定制填充单元的位置，数量和分布的方法。

6. 发明申请

US20080307383A1 ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN FOR ATTAINING POWER CLOSURE WHILE MAINTAINING EXISTING DESIGN CONSTRAINTS 失效
标题翻译：集成电路设计的迭代合成，用于在维护现有设计约束的情况下进行电源关闭
公开(公告)号：US20080307383A1
公开(公告)日：2008-12-11
申请号：US11759332
申请日：2007-06-07
申请人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译：描述了迭代地合成集成电路设计以获得功率闭合的方法。在一个实施例中，集成电路设计最初被合成以满足定时和功率约束。将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。

7. 发明授权

US07194715B2 Method and system for performing static timing analysis on digital electronic circuits 失效
标题翻译：在数字电子电路上执行静态时序分析的方法和系统
公开(公告)号：US07194715B2
公开(公告)日：2007-03-20
申请号：US10709376
申请日：2004-04-30
申请人： Steven E. Charlebois , Gerard M. Salem
发明人： Steven E. Charlebois , Gerard M. Salem
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file is converted to a group of cutpoints, and formal verification is performed on the cutpoints. A determination is made as to whether or not the cutpoints pass formal verification. If the cutpoints pass formal verification, the user analysis on the final circuit netlist is completed, and the final circuit netlist can proceed to manufacturing. Otherwise, if the cutpoints do not pass formal verification, a flag is issued to alert a user. The user then has to either modify certain snip point(s) within the snip file or modify the circuit netlist, and perform the user analysis again.
摘要翻译：公开了一种在数字电子电路上执行静态时序分析的方法。最初生成剪辑（或DC调整）文件。然后使用snip文件在最终的电路网表上执行静态时序分析。如果最终的电路网表满足所有的时序限制，则将snip文件转换成一组切点，并对切点执行形式验证。决定切点是否通过正式验证。如果切点通过正式验证，则完成最终电路网表上的用户分析，最后的电路网表可以进行制造。否则，如果切点没有通过正式验证，则会发出一个标志来提醒用户。然后，用户必须修改snip文件中的某些剪切点或修改电路网表，并再次执行用户分析。

8. 发明申请

US20090222772A1 Power Gating Logic Cones 有权
标题翻译：电源门控逻辑锥
公开(公告)号：US20090222772A1
公开(公告)日：2009-09-03
申请号：US12038845
申请日：2008-02-28
申请人： Steven E Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.
摘要翻译：描述了电源门控逻辑锥。在一个实施例中，一种方法包括用于集成电路（IC）设计的合成逻辑; 识别切换小于阈值的逻辑内的低交换节点; 基于所识别的低交换节点确定潜在功率门控锥（PGC）; 确定潜在PGC的功率选通逻辑表达式，其包括对最不切换的电位PGC的最小输入集合; 确定使用电源门控逻辑表达式的节能是否符合标准; 并接受潜在的PGC以满足标准。

9. 发明授权

US07444609B2 Method of optimizing customizable filler cells in an integrated circuit physical design process 有权
标题翻译：在集成电路物理设计过程中优化可定制填充单元的方法
公开(公告)号：US07444609B2
公开(公告)日：2008-10-28
申请号：US11427719
申请日：2006-06-29
申请人： Steven E. Charlebois , Paul E. Dunn , George W. Rohrbaugh, III
发明人： Steven E. Charlebois , Paul E. Dunn , George W. Rohrbaugh, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.
摘要翻译：一种用于在集成电路物理设计过程中优化可定制填充单元的系统和方法。特别地，本公开的填充单元布置算法用于在电路布局中优化可定制填充单元的方法中。填充单元布置算法执行在给定电路布局内选择起始点的操作，选择调整逻辑单元的位置的方向，调整逻辑单元的位置，从而组合填充单元以增加累积面积当形成可定制的填充单元时暂停调节操作; 并从新形成的可定制填充单元的点恢复调整操作。另外，提供了通过使用填充单元布置算法来优化集成电路设计中的可定制填充单元的位置，数量和分布的方法。

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