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1. 发明授权

US07158904B2 System and method for correcting an inaccurate clock 有权
标题翻译：用于校正不准确时钟的系统和方法
公开(公告)号：US07158904B2
公开(公告)日：2007-01-02
申请号：US11066375
申请日：2005-02-25
申请人： Sudhind Dhamankar , Srinivasan Venkatraman
发明人： Sudhind Dhamankar , Srinivasan Venkatraman
IPC分类号： G06F19/00
CPC分类号： G06F1/14
摘要： System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.
摘要翻译：使用精确的参考时钟校正不准确时钟的系统和方法。优选实施例包括：在每个指定时间段完成之后，在由指定时间段产生的时钟信号中产生的时钟信号中的时钟周期重复计数，基于时钟信号的时钟周期计数计算增量值累加Δ和值，以及基于Δ和值计算不准确时钟的时钟调整值。参考时钟用于标记每个指定时间段的结束。

2. 发明授权

US07051261B1 Turbo encoder with reduced processing delay 有权
标题翻译： Turbo编码器减少处理延迟
公开(公告)号：US07051261B1
公开(公告)日：2006-05-23
申请号：US10282524
申请日：2002-10-29
申请人： Sudhind Dhamankar
发明人： Sudhind Dhamankar
IPC分类号： H03M13/00 , H03M13/03 , G11C29/00
CPC分类号： H03M13/6505 , H03M13/2714 , H03M13/2771 , H03M13/2903 , H03M13/2957 , H03M13/6563
摘要： A turbo encoder includes a memory for temporarily storing an incoming data sequence and an interleaved address generator (IAG) designed to generate a sequence of addresses corresponding to the interleaved data sequence. The IAG performs calculations based on the length of the incoming data sequence and is able to generate a first interleaved address by (or before) the time the incoming data sequence has completely shifted into the memory. As a result, the encoder begins to output encoded data substantially as soon as the corresponding incoming data have been received, thus substantially reducing the processing delay. In addition, each interleaved address can be generated on the fly as needed during data output. As a result, the entire set of interleaved addresses does not need to be stored, thus reducing the memory requirements for the encoder.
摘要翻译：涡轮编码器包括用于临时存储输入数据序列的存储器和被设计用于生成对应于交错数据序列的地址序列的交织地址发生器（IAG）。 IAG基于输入数据序列的长度执行计算，并且能够通过（或之前）输入数据序列完全移入存储器的时间生成第一个交错地址。结果，一旦接收到相应的输入数据，编码器基本上开始输出编码数据，从而大大减少了处理延迟。此外，每个交错地址可以在数据输出期间按需生成。结果，整个交织地址集不需要被存储，从而减少了编码器的存储器要求。

3. 发明授权

US07032162B1 Polynomial expander for generating coefficients of a polynomial from roots of the polynomial 有权
标题翻译：多项式扩展器，用于从多项式的根生成多项式的系数
公开(公告)号：US07032162B1
公开(公告)日：2006-04-18
申请号：US10131883
申请日：2002-04-25
申请人： Sudhind Dhamankar
发明人： Sudhind Dhamankar
IPC分类号： H03M13/00
CPC分类号： H03M13/158 , H03M13/1515
摘要： For generating coefficients of an expanded polynomial, n-roots, each respective coefficient is generated at a respective one of (n+1) coefficient storage registers at one of a first place at a right most place to a (n+1) place at a left most place. In addition, a temporary coefficient is stored as the respective coefficient that was at the first place in a prior clock cycle. Such coefficients are initialized, and then an ith order multiplier output is generated by multiplying an ith order root with the respective coefficient at the first place, and an ith order adder output is generated by adding the temporary coefficient to the ith order multiplier output. The respective coefficients at and to the right of an (i+1) place are shifted toward the right with the respective coefficient at the first place becoming the temporary coefficient. The ith order adder output then becomes the respective coefficient at the (i+1) place. Such a process is performed an (i+1) times for the ith order root with (i+1) clock cycles and for each of the n-roots, for i=1 to n, to generate the respective coefficients of the expanded polynomial.
摘要翻译：为了产生扩展多项式的系数，n个根，在（n + 1）个位置的最右边的第一位置的（n + 1）个位置的第（n + 1）个系数存储寄存器的相应一个处生成每个相应的系数，一个最左边的地方。此外，临时系数被存储为在先前时钟周期中处于第一位置的相应系数。这样的系数被初始化，然后通过将第i个/次级根与第一个的相应系数相乘来产生第i个阶乘法器输出，并且i ^{阶乘法器输出来产生第次加法器输出。第（i + 1）个位置和右侧的各个系数在第一个地方的相应系数变为临时系数时向右移动。然后，第i个阶加法器输出变为第（i + 1）个位置的相应系数。对于具有（i + 1）时钟周期的第i个阶根，对于i = 1到n，对于n个根中的每一个，对于i（i + 1）次执行这样的处理，生成扩展多项式的相应系数。}

4. 发明授权

US08296714B2 System and method for checking analog circuit with digital checker 有权
标题翻译：用数字检查器检查模拟电路的系统和方法
公开(公告)号：US08296714B2
公开(公告)日：2012-10-23
申请号：US12580717
申请日：2009-10-16
申请人： Guha Lakshmanan , Sudhind Dhamankar , Vipin Sharma , Sandeep Tare
发明人： Guha Lakshmanan , Sudhind Dhamankar , Vipin Sharma , Sandeep Tare
IPC分类号： G06F17/50 , G06F11/22 , G01R31/02
CPC分类号： G01R31/31908
摘要： Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes establishing a target in the analog circuit, creating an analog target dummy for the target, creating a digital target dummy, binding the digital target dummy to the analog target dummy, and checking a value of the digital target dummy with a digital checker.
摘要翻译：本发明的方面提供一种使用数字检查器来检查模拟电路的一部分的系统和方法。该方法包括在模拟电路中建立目标，为目标产生模拟目标虚拟，产生数字目标虚拟，将数字目标虚拟与模拟目标虚拟相结合，并用数字检查器检查数字目标虚拟的值。

5. 发明申请

US20100097072A1 SYSTEM AND METHOD FOR CHECKING ANALOG CIRCUIT WITH DIGITAL CHECKER 有权
标题翻译：用数字检查器检测模拟电路的系统和方法
公开(公告)号：US20100097072A1
公开(公告)日：2010-04-22
申请号：US12580717
申请日：2009-10-16
申请人： Guha Lakshmanan , Sudhind Dhamankar , Sandeep Tare , Vipin Sharma
发明人： Guha Lakshmanan , Sudhind Dhamankar , Sandeep Tare , Vipin Sharma
IPC分类号： G01R31/02
CPC分类号： G01R31/31908
摘要： Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes establishing a target in the analog circuit, creating an analog target dummy for the target, creating a digital target dummy, binding the digital target dummy to the analog target dummy, and checking a value of the digital target dummy with a digital checker.
摘要翻译：本发明的方面提供一种使用数字检查器来检查模拟电路的一部分的系统和方法。该方法包括在模拟电路中建立目标，为目标产生模拟目标虚拟，产生数字目标虚拟，将数字目标虚拟与模拟目标虚拟相结合，并用数字检查器检查数字目标虚拟的值。

6. 发明授权

US07680472B2 Device and method for receiving and processing RF signals, a method for providing digital calibration values for such a device and a receiver incorporating the device 有权
标题翻译：用于接收和处理RF信号的装置和方法，用于为这种装置提供数字校准值的方法和结合该装置的接收器的方法
公开(公告)号：US07680472B2
公开(公告)日：2010-03-16
申请号：US11766530
申请日：2007-06-21
申请人： Sudhind Dhamankar , Naveen K. Yanduru
发明人： Sudhind Dhamankar , Naveen K. Yanduru
IPC分类号： H04B1/18 , H04B17/00
CPC分类号： H04B17/21
摘要： A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a digitally-tunable resonant circuit of the device, and a method of processing an RF signal. In one embodiment the device includes: (1) a low-noise amplifier having a digitally-tunable resonant circuit, (2) a memory configured to store digital calibration values particular to the device and (3) a time-constant controller coupled to the low-noise amplifier and configured to retrieve from the memory at least one of the digital calibration values as a function of a channel to be received and, based on the at least one, to cause the digitally-tunable resonant circuit to provide a time-constant corresponding to the channel to be received.
摘要翻译：一种用于在多个信道上接收RF信号的装置，包含该装置的接收机，为装置的数字可调谐谐振电路提供数字校准值的方法以及处理RF信号的方法。在一个实施例中，该装置包括：（1）具有数字可调谐谐振电路的低噪声放大器，（2）被配置为存储该设备特有的数字校准值的存储器，以及（3）耦合到该设备的时间常数控制器低噪声放大器，并且被配置为从所述存储器检索作为要接收的信道的函数的所述数字校准值中的至少一个，并且基于所述至少一个，使所述数字可调谐谐振电路提供时间 - 对应于要接收的通道的常数。

7. 发明申请

US20080318537A1 DEVICE AND METHOD FOR RECEIVING AND PROCESSING RF SIGNALS, A METHOD FOR PROVIDING DIGITAL CALIBRATION VALUES FOR SUCH A DEVICE AND A RECEIVER INCORPORATING THE DEVICE 有权
标题翻译：用于接收和处理RF信号的设备和方法，用于为这样的设备提供数字校准值的方法以及包含设备的接收器
公开(公告)号：US20080318537A1
公开(公告)日：2008-12-25
申请号：US11766530
申请日：2007-06-21
申请人： Sudhind Dhamankar , Naveen K. Yanduru
发明人： Sudhind Dhamankar , Naveen K. Yanduru
IPC分类号： H04B1/18
CPC分类号： H04B17/21
摘要： A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a digitally-tunable resonant circuit of the device, and a method of processing an RF signal. In one embodiment the device includes: (1) a low-noise amplifier having a digitally-tunable resonant circuit, (2) a memory configured to store digital calibration values particular to the device and (3) a time-constant controller coupled to the low-noise amplifier and configured to retrieve from the memory at least one of the digital calibration values as a function of a channel to be received and, based on the at least one, to cause the digitally-tunable resonant circuit to provide a time-constant corresponding to the channel to be received.
摘要翻译：一种用于在多个信道上接收RF信号的装置，包含该装置的接收机，为装置的数字可调谐谐振电路提供数字校准值的方法以及处理RF信号的方法。在一个实施例中，该装置包括：（1）具有数字可调谐谐振电路的低噪声放大器，（2）被配置为存储该设备特有的数字校准值的存储器，以及（3）耦合到该设备的时间常数控制器低噪声放大器，并且被配置为从所述存储器检索作为要接收的信道的函数的所述数字校准值中的至少一个，并且基于所述至少一个，使所述数字可调谐谐振电路提供时间 - 对应于要接收的通道的常数。

8. 发明申请

US20060195281A1 System and method for correcting an inaccurate clock 有权
标题翻译：用于校正不准确时钟的系统和方法
公开(公告)号：US20060195281A1
公开(公告)日：2006-08-31
申请号：US11066375
申请日：2005-02-25
申请人： Sudhind Dhamankar , Srinivasan Venkatraman
发明人： Sudhind Dhamankar , Srinivasan Venkatraman
IPC分类号： G06F19/00
CPC分类号： G06F1/14
摘要： System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.
摘要翻译：使用精确的参考时钟校正不准确时钟的系统和方法。优选实施例包括：在每个指定时间段完成之后，在由指定时间段产生的时钟信号中产生的时钟信号中的时钟周期重复计数，基于时钟信号的时钟周期计数计算增量值累加Δ和值，以及基于Δ和值计算不准确时钟的时钟调整值。参考时钟用于标记每个指定时间段的结束。

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