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1. 发明授权

US06511890B2 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06511890B2
公开(公告)日：2003-01-28
申请号：US09421090
申请日：1999-10-19
申请人： Sung-Kye Park , Young-Chul Lee
发明人： Sung-Kye Park , Young-Chul Lee
IPC分类号： H01L21331
CPC分类号： H01L21/76828 , H01L29/6659
摘要： The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer. The present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area of a semiconductor substrate of a first conductive type, forming a gate to the direction of device width wherein a gate oxide layer is inserted between the gate and semiconductor substrate, forming impurity regions in the semiconductor substrate at both sides of the gate by ion implantation with impurities of a second conductive type, forming an insulating interlayer covering the gate on the semiconductor substrate, and removing moisture contained in the insulating interlayer by thermal treatment.
摘要翻译：本发明涉及一种制造半导体器件的方法，该半导体器件防止由绝缘中间层中的水分导致的短沟道隆起。本发明包括以下步骤：在第一导电类型的半导体衬底的场区域中形成限定有源区的沟槽型场氧化物层，在器件宽度方向上形成栅极，其中栅氧化层插入在栅极和半导体衬底，通过具有第二导电类型的杂质的离子注入在栅极两侧的半导体衬底中形成杂质区，形成覆盖半导体衬底上的栅极的绝缘层，以及通过热处理。

2. 发明授权

US06479361B1 Isolation structure and fabricating method therefor 有权
标题翻译：隔离结构及其制造方法
公开(公告)号：US06479361B1
公开(公告)日：2002-11-12
申请号：US09527686
申请日：2000-03-17
申请人： Sung-Kye Park
发明人： Sung-Kye Park
IPC分类号： H01L21331
CPC分类号： H01L21/76224
摘要： A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.
摘要翻译：公开了一种半导体器件隔离结构及其制造方法。隔离结构包括形成在隔离区域上以限定有源区的沟槽。第一，第二和第三绝缘层沉积在沟槽中。第二绝缘层具有与第一绝缘层和第三绝缘层不同的蚀刻选择比。与沟槽的侧壁接触的第三绝缘层的边缘部分特征性地不显示任何塌陷。因此，当提供亚阈值电压时，不会产生驼峰现象。结果，防止漏电流增加，并且可以防止器件刷新特性恶化。此外，第三绝缘层覆盖沟槽的顶部边缘部分。因此，栅极绝缘层（稍后形成）具有足够的厚度。因此，可以防止屈服电压特性恶化。

3. 发明授权

US06326665B1 Semiconductor device with insulating films 有权
标题翻译：具有绝缘膜的半导体器件
公开(公告)号：US06326665B1
公开(公告)日：2001-12-04
申请号：US09570787
申请日：2000-05-15
申请人： Sung Kye Park , Eun Jeong Shin
发明人： Sung Kye Park , Eun Jeong Shin
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L29/0653
摘要： A semiconductor device and a method for fabricating the same are disclosed that reduce short channel effects to improve device characteristics. The semiconductor device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film and a lightly doped region formed in the semiconductor substrate at both sides of the gate electrode. A sidewall insulating film is formed at both sides of the gate electrode and a heavily doped impurity region is formed in the semiconductor substrate extending from the sidewall insulating film. Further, an insulating film is formed at sides of the heavily doped impurity region. The insulating film prevents impurity ions from the heavily doped impurity region from diffusing into the channel region of the device.
摘要翻译：公开了半导体器件及其制造方法，其减少短沟道效应以改善器件特性。半导体器件包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和形成在栅电极两侧的半导体衬底中的轻掺杂区域。在栅电极的两侧形成侧壁绝缘膜，并且在从侧壁绝缘膜延伸的半导体衬底中形成重掺杂杂质区。此外，在重掺杂杂质区域的侧面形成绝缘膜。绝缘膜防止重掺杂杂质区域的杂质离子扩散到器件的沟道区域。

4. 发明授权

US08675404B2 Reading method of non-volatile memory device 有权
标题翻译：非易失性存储器件的读取方法
公开(公告)号：US08675404B2
公开(公告)日：2014-03-18
申请号：US13475204
申请日：2012-05-18
申请人： Hyun-Seung Yoo , Sung-Joo Hong , Seiichi Aritome , Seok-Kiu Lee , Sung-Kye Park , Gyu-Seog Cho , Eun-Seok Choi , Han-Soo Joo
发明人： Hyun-Seung Yoo , Sung-Joo Hong , Seiichi Aritome , Seok-Kiu Lee , Sung-Kye Park , Gyu-Seog Cho , Eun-Seok Choi , Han-Soo Joo
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3418
摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.
摘要翻译：一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始，所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替。

5. 发明授权

US06693018B2 Method for fabricating DRAM cell transistor having trench isolation structure 失效
标题翻译：制造具有沟槽隔离结构的DRAM单元晶体管的方法
公开(公告)号：US06693018B2
公开(公告)日：2004-02-17
申请号：US10330617
申请日：2002-12-27
申请人： Hee Sang Kim , Sung Kye Park
发明人： Hee Sang Kim , Sung Kye Park
IPC分类号： H01L218242
CPC分类号： H01L21/763 , H01L21/76232 , H01L27/10873
摘要： The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film. Thus, a back bias is applied to the well region, and at the same time, also applied to the electrode formed within the field oxide film, so that the electric potential at the edge portion of the field oxide film is increased and the potential barrier between the junction region and the channel region is increased, thereby improving the punch-through characteristic.
摘要翻译：本发明涉及一种用于制造具有沟槽隔离结构的DRAM单元晶体管的方法，其可以防止有效沟道长度的减小和场氧化膜边缘部分的穿通特性的劣化，这是导致的通过由于由场氧化膜引起的硼偏析效应，由于场氧化膜边缘部分的沟道掺杂浓度降低而导致的结区域和沟道区域之间的势垒的减小，相比之下到通道区域的中心部分。根据本发明的方法，在场氧化物膜内形成具有与阱区相同的导电类型的电极结构。因此，向阱区域施加反向偏压，并且同时也施加到形成在场氧化膜内的电极，使得场氧化膜的边缘部分处的电位增加，势垒在接合区域和沟道区域之间增加，从而提高穿透特性。

6. 发明授权

US06215153B1 MOSFET and method for fabricating the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US06215153B1
公开(公告)日：2001-04-10
申请号：US09235747
申请日：1999-01-25
申请人： Sung Kye Park
发明人： Sung Kye Park
IPC分类号： H01L31119
CPC分类号： H01L29/6659 , H01L29/0653 , H01L29/7833
摘要： Barrier layers of an insulating material block the diffusion of the halo ions to an edge portion of the gate electrode, the halo ions being injected for improving short channel characteristic. The barrier layers prevent an increase of a threshold voltage of the device and improve electrical characteristics of the device.
摘要翻译：绝缘材料的阻挡层阻止卤素离子扩散到栅电极的边缘部分，注入卤离子以改善短沟道特性。阻挡层防止器件的阈值电压的增加并改善器件的电气特性。

7. 发明授权

US6166447A Semiconductor memory device having first and second voltage level shifters 失效
标题翻译：具有第一和第二电压电平转换器的半导体存储器件
公开(公告)号：US6166447A
公开(公告)日：2000-12-26
申请号：US932378
申请日：1997-09-17
申请人： Sung Kye Park
发明人： Sung Kye Park
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/904
摘要： A memory device of the present invention provides a stable operation and low voltage characteristics. An access device receives first and second data signals on first and second data lines, respectively, and is coupled to first and second nodes. A drive device is coupled to the access device at the first and second nodes. A voltage shifting device is coupled to at least one of the first and second nodes to change a voltage of at least one of the first and second nodes. The access device includes a first access transistor coupled to the first data line and the first node. The access device also includes a second access transistor coupled to the second data line and the second node. The first and second access transistors are responsive to a control signal. The drive device includes a first resistive element coupled to the first node, a second resistive element coupled to the second node, a first drive transistor coupled to the first and second nodes, and a second drive transistor coupled to the first and second nodes. The voltage shifting device includes a first voltage shifter coupled to the first node such that the first voltage shifter changes a first node voltage level, and a second voltage shifter coupled to the second node such that the second voltage shifter changes a second node voltage level.
摘要翻译：本发明的存储器件提供稳定的操作和低电压特性。接入设备分别在第一和第二数据线上接收第一和第二数据信号，并且耦合到第一和第二节点。驱动设备在第一和第二节点处耦合到接入设备。电压移位装置耦合到第一和第二节点中的至少一个以改变第一和第二节点中的至少一个节点的电压。接入设备包括耦合到第一数据线和第一节点的第一存取晶体管。接入设备还包括耦合到第二数据线和第二节点的第二存取晶体管。第一和第二存取晶体管响应于控制信号。驱动装置包括耦合到第一节点的第一电阻元件，耦合到第二节点的第二电阻元件，耦合到第一和第二节点的第一驱动晶体管，以及耦合到第一和第二节点的第二驱动晶体管。电压移位装置包括耦合到第一节点的第一电压移位器，使得第一电压移位器改变第一节点电压电平，以及耦合到第二节点的第二电压移位器，使得第二电压移位器改变第二节点电压电平。

8. 发明授权

US6091106A Low voltage transistor structure having a grooved gate 失效
标题翻译：具有沟槽栅极的低压晶体管结构
公开(公告)号：US6091106A
公开(公告)日：2000-07-18
申请号：US957781
申请日：1997-10-24
申请人： Sung Kye Park
发明人： Sung Kye Park
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/76
CPC分类号： H01L27/1112 , H01L29/66575 , H01L29/78
摘要： Disclosed is a transistor structure having a semiconductor substrate with a active region and a field region, a recess region being defined by either the field region or the active region, a gate electrode formed on portions of the active and recess region, and impurity regions formed in the active region of the semiconductor substrate on either side of the gate electrode. The transistor structure has an active region with at least one groove formed therein, and the transistor structure being formed for a low voltage operation.
摘要翻译：公开了一种晶体管结构，其具有具有有源区和场区的半导体衬底，由场区域或有源区域限定的凹陷区域，形成在有源区和凹区的部分上的栅电极和形成的杂质区在栅电极两侧的半导体衬底的有源区中。晶体管结构具有其中形成有至少一个沟槽的有源区，并且晶体管结构形成为用于低电压操作。

9. 发明授权

US5952677A Thin film transistor and method for manufacturing the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US5952677A
公开(公告)日：1999-09-14
申请号：US73869
申请日：1998-05-07
申请人： Sung Kye Park
发明人： Sung Kye Park
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66765 , H01L29/78624
摘要： A thin film transistor (TFT) and a method for manufacturing the same suitable for improving device characteristics by using a self-align technology are disclosed, the TFT including a substrate; a gate electrode having first and second sides on the substrate; a first conductive layer pattern formed on the substrate, wherein between the first conductive layer pattern and the first side of the gate electrode is a sidewall spacer; the sidewall spacer; a second conductive layer pattern formed on the substrate to be connected to the first conductive layer pattern; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer, the sidewall spacer, the first conductive layer pattern, and the substrate; a source region formed in the active layer at the second side of the gate electrode; and a drain region formed on the active layer on the first conductive layer pattern.
摘要翻译：公开了一种薄膜晶体管（TFT）及其制造方法，其适用于通过使用自对准技术来提高器件特性，该TFT包括衬底; 栅电极，在基板上具有第一和第二面; 形成在所述基板上的第一导电层图案，其中在所述第一导电层图案和所述栅电极的所述第一侧之间是侧壁间隔物; 侧壁间隔件; 形成在所述基板上以连接到所述第一导电层图案的第二导电层图案; 形成在所述栅电极上的栅极绝缘层; 形成在所述栅极绝缘层，所述侧壁间隔物，所述第一导电层图案和所述基板上的有源层; 源极区，形成在所述栅电极的第二侧的有源层中; 以及形成在第一导电层图案上的有源层上的漏极区域。

10. 发明授权

US07176722B2 Low power high performance inverter circuit 失效
标题翻译：低功耗高性能逆变电路
公开(公告)号：US07176722B2
公开(公告)日：2007-02-13
申请号：US11032534
申请日：2005-01-10
申请人： Sung Kye Park , Choon Sik Oh
发明人： Sung Kye Park , Choon Sik Oh
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , H03K19/01707
摘要： A low-power, high-performance inverter circuit comprises first and second inverter circuit portions. The first portion comprises a first inverter, including a first pull-up element and a first pull-down element, for inverting an input signal, a first switching element connected between the first pull-down element and ground for switching the first inverter, and a first diode connected between the first pull-down element and ground in parallel with the first switching element. The second portion comprises a second inverter, including a second pull-up element and a second pull-down element, for inverting an input signal, a second switching element connected between the second pull-up element and a supply voltage terminal for switching the second inverter, and a second diode connected between the second pull-up element and the supply voltage terminal in parallel with the second switching element. An output of the first portion is connected to an input of the second portion.
摘要翻译：低功率，高性能的逆变器电路包括第一和第二逆变器电路部分。第一部分包括第一反相器，包括用于反相输入信号的第一上拉元件和第一下拉元件，连接在第一下拉元件和地之间的用于切换第一反相器的第一开关元件，以及连接在第一下拉元件与第一开关元件并联的第一二极管。第二部分包括第二反相器，包括用于反相输入信号的第二上拉元件和第二下拉元件;连接在第二上拉元件和电源电压端子之间的第二开关元件，用于切换第二逆变器和与第二开关元件并联连接在第二上拉元件和电源电压端子之间的第二二极管。第一部分的输出连接到第二部分的输入端。

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