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1. 发明授权

US06828193B2 Methods of forming hemispherical grained silicon on a template on a semiconductor work object 失效
公开(公告)号：US06828193B2
公开(公告)日：2004-12-07
申请号：US10174696
申请日：2002-06-18
申请人： Guoqing Chen , James Pan
发明人： Guoqing Chen , James Pan
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L28/90
摘要： The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

2. 发明授权

US06828192B2 Semiconductor memory cell and method for fabricating the memory cell 失效
标题翻译：半导体存储单元及其制造方法
公开(公告)号：US06828192B2
公开(公告)日：2004-12-07
申请号：US10657928
申请日：2003-09-10
申请人： Wolfgang Gustin , Ulrike Grüning-Von Schwerin , Dietmar Temmler , Martin Schrems , Stefan Rongen , Rudolf Strasser
发明人： Wolfgang Gustin , Ulrike Grüning-Von Schwerin , Dietmar Temmler , Martin Schrems , Stefan Rongen , Rudolf Strasser
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10873
摘要： A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.
摘要翻译：在沟槽中形成沟槽电容器，其设置在基板中。沟槽填充有用作内部电容器电极的导电沟槽填充物。在衬底上的沟槽的侧壁上生长外延层。掩埋带设置在填充有第二中间层的导电沟槽和外延生长层之间。在外延生长层中设置从掩埋带形成的掺杂剂外扩散。通过外延生长层，从布置在沟槽旁边的选择晶体管进一步去除掺杂剂扩散，结果可以避免选择晶体管中的短沟道效应。

3. 发明授权

US06828190B2 Method for manufacturing capacitor of semiconductor device having dielectric layer of high dielectric constant 有权
标题翻译：具有介电常数高的半导体器件的电容器的制造方法
公开(公告)号：US06828190B2
公开(公告)日：2004-12-07
申请号：US09276803
申请日：1999-03-26
申请人： Byoung-taek Lee , Ki-hoon Lee
发明人： Byoung-taek Lee , Ki-hoon Lee
IPC分类号： H01L218242
CPC分类号： H01L28/82
摘要： A method of manufacturing a capacitor includes sequentially forming a storage electrode, a high dielectric layer, a plate electrode, and an interdielectric layer over a semiconductor substrate. A first post-annealing of the substrate is performed under an inert atmosphere at a first temperature, and then a second post-annealing is performed at a second temperature. The first and second post annealings can be performed after forming the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination thereof, as long as the second post-annealing is performed after the first post-annealing. The post-annealings are not necessarily performed in a same place or stage. The first temperature may be about 600° C. to 900° C., and the second temperature about 100° C. to 600° C. As a result, the dielectric constant of the high dielectric layer is increased, and leakage current is reduced.
摘要翻译：制造电容器的方法包括在半导体衬底上顺序形成存储电极，高电介质层，平板电极和电介质层。在第一温度下在惰性气氛下进行基材的第一次后退火，然后在第二温度下进行第二次后退火。第一和第二后退火可以在形成高介电层，平板电极或介电层之后进行，或者其任何组合，只要在第一次后退火之后进行第二次后退火即可。后退火不一定在相同的地方或阶段进行。第一温度可以为约600℃至900℃，第二温度为约100℃至600℃。结果，高介电层的介电常数增加，泄漏电流降低。

4. 发明授权

US06828160B2 Method of forming ferroelectric random access memory cell 有权
标题翻译：形成铁电随机存取存储单元的方法
公开(公告)号：US06828160B2
公开(公告)日：2004-12-07
申请号：US10165961
申请日：2002-06-11
申请人： Haochieh Liu
发明人： Haochieh Liu
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159
摘要： A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.
摘要翻译： MFMIS存储器件设置有仅使用一个字线掩模形成的倒置的T形栅极堆叠。 MFMIS存储器件使用形成字线的一个字线掩模形成，并且使用间隔件形成与自对准蚀刻工艺兼容的反向T形栅极叠层。

5. 发明授权

US06825094B2 Method for increasing capacitance of deep trench capacitors 有权
标题翻译：增加深沟槽电容器电容的方法
公开(公告)号：US06825094B2
公开(公告)日：2004-11-30
申请号：US10628895
申请日：2003-07-28
申请人： Chang-Rong Wu , Yi-Nan Chen
发明人： Chang-Rong Wu , Yi-Nan Chen
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L27/10864 , H01L27/10867
摘要： A method for increasing the capacitance of deep trench capacitors. The method includes providing a substrate, forming a pad structure on the substrate, forming a photoresist defining the region of the deep trench on the pad structure, forming a deep trench in the substrate, removing the photoresist, forming a capacitor in the lower portion of the deep trench, forming a first insulation layer on the capacitor, forming an epitaxy layer on the sidewall of the deep trench above the first insulation layer as a liner to narrow the dimension of the deep trench, and removing the first insulation layer uncovered by the epitaxy layer.
摘要翻译：一种增加深沟槽电容器电容的方法。该方法包括提供衬底，在衬底上形成衬垫结构，形成限定衬垫结构上的深沟槽区域的光致抗蚀剂，在衬底中形成深沟槽，去除光致抗蚀剂，在下部形成电容器所述深沟槽在所述电容器上形成第一绝缘层，在所述第一绝缘层上方的所述深沟槽的侧壁上形成外延层作为衬垫，以使所述深沟槽的尺寸变窄，以及去除由所述第一绝缘层未覆盖的所述第一绝缘层外延层。

6. 发明授权

US06825077B2 Method of forming memory cells and a method of isolating a single row of memory cells 失效
标题翻译：形成存储单元的方法和隔离单行存储单元的方法
公开(公告)号：US06825077B2
公开(公告)日：2004-11-30
申请号：US10713647
申请日：2003-11-13
申请人： Luan C. Tran
发明人： Luan C. Tran
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/0214 , H01L27/10894 , Y10S257/906 , Y10S438/981
摘要： The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.
摘要翻译：本发明包括形成在半导体衬底上的6F 2 DRAM阵列。存储器阵列包括第一存储单元。第一存储单元包括第一存取晶体管和第一数据存储电容器。第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。存储器阵列还包括第二存储器单元。第二存储单元包括第二存取晶体管和第二数据存储电容器。第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。第一和第二存取晶体管具有具有第一厚度的栅极电介质。存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。隔离栅极具有第二厚度大于第一厚度的栅极电介质。隔离栅极电介质可以在衬底的表面上方或下方延伸。

7. 发明授权

US06818496B2 Silicon on insulator DRAM process utilizing both fully and partially depleted devices 有权
标题翻译：使用完全和部分耗尽的器件的绝缘体上硅DRAM工艺
公开(公告)号：US06818496B2
公开(公告)日：2004-11-16
申请号：US10265426
申请日：2002-10-07
申请人： Charles H. Dennison , John K. Zahurak
发明人： Charles H. Dennison , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/3081 , H01L21/31111 , H01L21/31116 , H01L21/84 , H01L27/10811 , H01L27/10873 , H01L27/1203
摘要： This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.
摘要翻译：本发明涉及半导体集成电路领域，特别涉及制造在绝缘体上硅（SOI）衬底和器件上的独立和嵌入式存储器芯片。部分耗尽（PD）和完全耗尽（FD）器件在同一芯片上被利用。本发明是在芯片的一个区域中利用完全耗尽的SOI器件和在芯片的选定其他区域中部分耗尽的SOI器件的工艺流程。完全耗尽或部分耗尽的选择仅由芯片的该特定区域中的电路应用决定。本发明能够根据DRAM处理，特别是具有大比例的相关逻辑电路的嵌入式DRAM。

8. 发明授权

US06815288B2 Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof 有权
公开(公告)号：US06815288B2
公开(公告)日：2004-11-09
申请号：US10623587
申请日：2003-07-22
申请人： Bong-seok Kim
发明人： Bong-seok Kim
IPC分类号： H01L218242
CPC分类号： H01L21/8238 , H01L27/10894
摘要： A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

9. 发明授权

US06808980B2 Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices 有权
标题翻译：过程简化的方法和消除创建高级1T-RAM器件的地形问题
公开(公告)号：US06808980B2
公开(公告)日：2004-10-26
申请号：US10310486
申请日：2002-12-05
申请人： Chung-Yi Chen , Min-Hsiung Chiang , Hsien-Yuan Chang
发明人： Chung-Yi Chen , Min-Hsiung Chiang , Hsien-Yuan Chang
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A new method and structure is provided for the creation of a 1T-RAM cell. Shallow Trench Isolation (STI) regions are provided over a substrate. A 3D capacitor area is defined over the substrate, a patterned layer of polysilicon or HSG polysilicon is created aligned with the 3D capacitor area, providing the bottom plate of a 3D capacitor. Gate oxide is grown to form a dielectric for CMOS gate electrodes and the 3D capacitor dielectric. A patterned layer of polysilicon is created, defining gate electrodes and 3D capacitor upper plates.
摘要翻译：提供了一种新的方法和结构来创建1T-RAM单元。在衬底上提供浅沟槽隔离（STI）区域。三维电容器区域被限定在衬底上，多晶硅或HSG多晶硅的图案化层被创建成与3D电容器区域对准，从而提供3D电容器的底板。生长栅极氧化物以形成用于CMOS栅电极和3D电容器电介质的电介质。产生多晶硅图案层，限定栅电极和3D电容器上板。

10. 发明授权

US06806137B2 Trench buried bit line memory devices and methods thereof 有权
标题翻译：沟槽掩埋位线存储器件及其方法
公开(公告)号：US06806137B2
公开(公告)日：2004-10-19
申请号：US10705707
申请日：2003-11-11
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译：诸如6F 2存储器件的存储器件包括大致平行于并沿着有源区的相关带形成的隔离沟槽。导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

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