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1. 发明申请

US20110101443A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110101443A1
公开(公告)日：2011-05-05
申请号：US12894615
申请日：2010-09-30
申请人： ZongLiang HUO , Myoungbum LEE , Kihyun HWANG , Seungmok SHIN , Sunjung KIM
发明人： ZongLiang HUO , Myoungbum LEE , Kihyun HWANG , Seungmok SHIN , Sunjung KIM
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , H01L29/7926
摘要： Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。层叠结构可以设置在半导体衬底上。层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。半导体图案可以通过层叠结构连接到半导体衬底。信息存储层可以设置在半导体图案和导电图案之间。固定电荷层可以设置在半导体图案和层间电介质图案之间。固定电荷层可以包括固定电荷。固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

2. 发明申请

US20090039415A1 Method of forming dielectric including dysprosium and scandium by atomic layer deposition and integrated circuit device including the dielectric layer 有权
标题翻译：通过原子层沉积形成包括镝和钪的电介质的方法和包括电介质层的集成电路器件
公开(公告)号：US20090039415A1
公开(公告)日：2009-02-12
申请号：US12153952
申请日：2008-05-28
申请人： Hoonsang Choi , Bongjin Kuh , Sunjung Kim , Youngsun Kim , Seunghwan Lee , Sangwook Lim , Chunhyung Chung
发明人： Hoonsang Choi , Bongjin Kuh , Sunjung Kim , Youngsun Kim , Seunghwan Lee , Sangwook Lim , Chunhyung Chung
IPC分类号： H01L21/28 , H05K3/00 , H01L29/792 , C23C16/00
CPC分类号： H01L29/513 , C23C16/40 , C23C16/45531 , C23C16/45553 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L29/517 , H01L29/78
摘要： In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.
摘要翻译：在一个实施例中，形成电介质层的方法包括在小于400摄氏度的温度下向包括衬底的腔室供应第一前体。第一个前体包括镝。将第一反应气体供应到室以与第一前体反应。在小于400摄氏度的温度下将第二前体供应到室，并且第二前体包括钪。将第二反应气体供应到室以与第二前体反应。

3. 发明授权

US10593801B2 Semiconductor devices and methods of fabricating the same 有权
公开(公告)号：US10593801B2
公开(公告)日：2020-03-17
申请号：US15062553
申请日：2016-03-07
申请人： Tae-Jong Lee , Sanghyuk Hong , TaeYong Kwon , Sunjung Kim , Cheol Kim
发明人： Tae-Jong Lee , Sanghyuk Hong , TaeYong Kwon , Sunjung Kim , Cheol Kim
IPC分类号： H01L29/78 , H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/66 , H01L21/8238
摘要： Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

4. 发明申请

US20160336450A1 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS 有权
标题翻译：包括场效应晶体管的半导体器件
公开(公告)号：US20160336450A1
公开(公告)日：2016-11-17
申请号：US15093892
申请日：2016-04-08
申请人： Yong-Suk TAK , Jongryeol YOO , Hyun Jung LEE , Miseon PARK , Bonyoung KOO , Sunjung KIM
发明人： Yong-Suk TAK , Jongryeol YOO , Hyun Jung LEE , Miseon PARK , Bonyoung KOO , Sunjung KIM
IPC分类号： H01L29/78 , H01L29/08
CPC分类号： H01L29/7851 , H01L29/0847 , H01L29/165 , H01L29/66545 , H01L29/7848 , H01L29/7849
摘要： A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.
摘要翻译：半导体器件包括在衬底上并沿第一方向延伸的翅片结构，在翅片结构上交叉的栅电极，在栅电极的相对侧的翅片结构上的源/漏区和鳍结构之间的阻挡层和源极/漏极区域中的每一个。翅片结构包括具有与衬底的晶格常数不同的晶格常数的材料，鳍结构，源极/漏极区和阻挡层包括锗，并且阻挡层中的锗浓度大于鳍结构中的锗浓度并且在每个源极/漏极区域中小于最大锗浓度。

5. 发明授权

US08283719B2 Nonvolatile memory device having a fixed charge layer 有权
标题翻译：具有固定电荷层的非易失性存储器件
公开(公告)号：US08283719B2
公开(公告)日：2012-10-09
申请号：US12894615
申请日：2010-09-30
申请人： ZongLiang Huo , Myoungbum Lee , Kihyun Hwang , Seungmok Shin , Sunjung Kim
发明人： ZongLiang Huo , Myoungbum Lee , Kihyun Hwang , Seungmok Shin , Sunjung Kim
IPC分类号： H01L29/792 , H01L29/788 , H01L29/76
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , H01L29/7926
摘要： Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。层叠结构可以设置在半导体衬底上。层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。半导体图案可以通过层叠结构连接到半导体衬底。信息存储层可以设置在半导体图案和导电图案之间。固定电荷层可以设置在半导体图案和层间电介质图案之间。固定电荷层可以包括固定电荷。固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

6. 发明授权

US07528416B2 Vertical structure LED and fabricating method thereof 有权
标题翻译：垂直结构LED及其制造方法
公开(公告)号：US07528416B2
公开(公告)日：2009-05-05
申请号：US11476627
申请日：2006-06-29
申请人： Sunjung Kim , Hyunjae Lee , Geunho Kim
发明人： Sunjung Kim , Hyunjae Lee , Geunho Kim
IPC分类号： H01L27/15 , H01L21/00
CPC分类号： H01L33/0079 , H01L33/40 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49107 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： A vertical structure light emitting diode (LED) and a fabricating method thereof is disclosed, wherein a metal support layer is formed on an upper surface of a light emitting structure by way of electrolytic plating method in which no high temperature process is required to obviate occurrence of defects on the devices, and the metal support layer containing a soft metal and a hard metal is formed on the light emitting structure to prevent occurrence of warping of a wafer to increase the mechanical strength and to improve reliability.
摘要翻译：公开了一种垂直结构发光二极管（LED）及其制造方法，其中通过不需要高温处理以消除发生的电解电镀方法在发光结构的上表面上形成金属支撑层在发光结构上形成包含软金属和硬金属的金属支撑层，以防止晶片翘曲发生，从而提高机械强度并提高可靠性。

7. 发明授权

US09577043B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09577043B2
公开(公告)日：2017-02-21
申请号：US14826174
申请日：2015-08-13
申请人： Jongryeol Yoo , Hyun Jung Lee , Sunjung Kim , Seung Hun Lee , Eunhye Choi
发明人： Jongryeol Yoo , Hyun Jung Lee , Sunjung Kim , Seung Hun Lee , Eunhye Choi
IPC分类号： H01L29/10 , H01L29/165 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L27/088 , H01L21/8234
CPC分类号： H01L29/1054 , H01L21/823412 , H01L21/823814 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/165 , H01L29/7849
摘要： A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium. A germanium concentration difference between the first and second channel layers is greater than a germanium concentration difference between the buffer layer and the second channel layer. The spacer layer has a germanium concentration gradient.
摘要翻译：半导体器件包括在半导体衬底上的包括第一和第二区域的缓冲层，第一区域的缓冲层上的第一沟道层，第二区域的缓冲层上的第二沟道层以及第二区域之间的间隔层通道层和缓冲层。缓冲层，第一和第二沟道层以及间隔层由包括锗的半导体材料形成。第一和第二沟道层之间的锗浓度差大于缓冲层和第二沟道层之间的锗浓度差。间隔层具有锗浓度梯度。

8. 发明申请

US20160315081A1 SEMICONDUCTOR DEVICE HAVING FIN ACTIVE REGIONS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有精细活性区域的半导体器件及其制造方法
公开(公告)号：US20160315081A1
公开(公告)日：2016-10-27
申请号：US15013969
申请日：2016-02-02
申请人： Miseon PARK , Jongryeol YOO , Hyunjung LEE , Yong-Suk TAK , Bonyoung KOO , Sunjung KIM
发明人： Miseon PARK , Jongryeol YOO , Hyunjung LEE , Yong-Suk TAK , Bonyoung KOO , Sunjung KIM
IPC分类号： H01L27/088 , H01L29/417 , H01L29/08 , H01L29/06 , H01L29/161
CPC分类号： H01L27/0886 , H01L21/823425 , H01L21/823431 , H01L29/0649 , H01L29/0847 , H01L29/161 , H01L29/41791
摘要： A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.
摘要翻译：半导体器件可以包括在衬底上彼此平行延伸的翅片有源区域，翅片有源区域之间的隔离区域，与翅片有源区域相交并且彼此平行延伸的栅极图案，翅片有源区域之间的源极/漏极区域在所述栅极图案和鳍状有源区间隔物接触所述翅片有源区域的侧表面并形成在所述鳍片活动区域之间的所述隔离区域的表面上。翅片有源区间隔物的最上层可以高于翅片有源区和源极/漏极区之间的界面。隔离区域的上表面可以低于源/漏区域的底表面。

9. 发明申请

US20160104775A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160104775A1
公开(公告)日：2016-04-14
申请号：US14826174
申请日：2015-08-13
申请人： JONGRYEOL YOO , HYUN JUNG LEE , SUNJUNG KIM , SEUNG HUN LEE , Eunhye CHOI
发明人： JONGRYEOL YOO , HYUN JUNG LEE , SUNJUNG KIM , SEUNG HUN LEE , Eunhye CHOI
IPC分类号： H01L29/10 , H01L29/78 , H01L21/8234 , H01L29/165 , H01L27/088
CPC分类号： H01L29/1054 , H01L21/823412 , H01L21/823814 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/165 , H01L29/7849
摘要： A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium. A germanium concentration difference between the first and second channel layers is greater than a germanium concentration difference between the buffer layer and the second channel layer. The spacer layer has a germanium concentration gradient.
摘要翻译：半导体器件包括在半导体衬底上的包括第一和第二区域的缓冲层，第一区域的缓冲层上的第一沟道层，第二区域的缓冲层上的第二沟道层以及第二区域之间的间隔层通道层和缓冲层。缓冲层，第一和第二沟道层以及间隔层由包括锗的半导体材料形成。第一和第二沟道层之间的锗浓度差大于缓冲层和第二沟道层之间的锗浓度差。间隔层具有锗浓度梯度。

10. 发明申请

US20150311887A1 ANALOG SIGNAL GENERATION CIRCUIT 有权
标题翻译：模拟信号发生电路
公开(公告)号：US20150311887A1
公开(公告)日：2015-10-29
申请号：US14694409
申请日：2015-04-23
申请人： Sunjung KIM , Taechan KIM , Seunghoon LEE
发明人： Sunjung KIM , Taechan KIM , Seunghoon LEE
IPC分类号： H03K3/356
CPC分类号： H04N5/378 , H03M1/1295 , H03M1/56
摘要： An analog signal generation circuit is provided. The analog signal generation circuit includes a first control section that generates a first control signal; a second control section that generates a second control signal; current cells, each of the plurality of current cells controlled to generate current or to not generate current based on the first and second control signals; and an analog signal output section that outputs an analog signal generated based on current generated by the current cells. The first control signal includes first and second cell state setting signals. A logical value corresponding to the first cell state setting signal is complementary to a logical value corresponding to the second cell state setting signal. Each current cell has an initialized state based on the first cell state setting signal.
摘要翻译：提供模拟信号发生电路。模拟信号发生电路包括产生第一控制信号的第一控制部分; 产生第二控制信号的第二控制部分; 所述多个当前单元中的每一个被控制为基于所述第一和第二控制信号产生电流或不产生电流; 以及模拟信号输出部，其输出基于当前单元产生的电流而生成的模拟信号。第一控制信号包括第一和第二单元状态设置信号。对应于第一单元状态设置信号的逻辑值与对应于第二单元状态设置信号的逻辑值互补。每个当前单元基于第一单元状态设置信号具有初始化状态。

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