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1. 发明申请

US20160300839A1 INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译：集成电路和半导体器件
公开(公告)号：US20160300839A1
公开(公告)日：2016-10-13
申请号：US15093504
申请日：2016-04-07
申请人： Ha-young Kim , Sung-we Cho , Tae-joong Song , Sang-hoon Baek
发明人： Ha-young Kim , Sung-we Cho , Tae-joong Song , Sang-hoon Baek
IPC分类号： H01L27/092 , H01L23/522 , H01L27/02 , H01L23/528
CPC分类号： H01L27/0924 , G06F17/5077 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/0207 , H01L27/092
摘要： An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.
摘要翻译：实施例包括包括标准单元的集成电路，该标准单元包括：具有不同导电类型并沿第一方向延伸的第一和第二有源区; 第一，第二和第三导电线在基本上垂直于第一方向的第二方向上在第一和第二有源区上延伸并彼此平行设置; 以及切割层，其在所述第一和第二有源区域之间沿所述第一方向延伸，并且将所述第一导电线分离成第一上导电线和第一下导电线，所述第二导线变为第二上导电线和第二下导电线线和第三导线插入第三上导电线和第三下导电线; 其中：所述第一上导电线和所述第三下导电线电连接在一起; 并且第二上导线和第二下导电线电连接在一起。

2. 发明申请

US20120206988A1 NEGATIVE VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：负电压发生器和半导体存储器件
公开(公告)号：US20120206988A1
公开(公告)日：2012-08-16
申请号：US13358121
申请日：2012-01-25
申请人： Tae-Joong Song , Gyu-Hong Kim , Jae-Seung Choi , Soung-Hoon Sim , In-Gyu Park , Chan-Ho Lee , Hyun-Su Choi , Jong-Hoon Jung
发明人： Tae-Joong Song , Gyu-Hong Kim , Jae-Seung Choi , Soung-Hoon Sim , In-Gyu Park , Chan-Ho Lee , Hyun-Su Choi , Jong-Hoon Jung
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C11/419 , G11C5/145 , G11C7/12
摘要： A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.
摘要翻译：负电压发生器包括可变电容负电压产生单元，开关单元和正电压施加单元。负电压产生单元包括用于改变负电压被充电的电容的多个耦合电容器。负电压产生单元根据写入数据的存储体组的行数（大小）选择多个耦合电容器中的至少一个耦合电容器，并将至少一个所选择的耦合电容器充电至负电压。切换单元响应于数据选择具有互补的第一和第二位线的位线对的一个位线，并且将至少一个选择的耦合电容器连接到所选择的位线。正电压施加单元将正（高）电压施加到位线对的另一位线。

3. 发明申请

US20060002223A1 SRAM employing virtual rail scheme stable against various process-voltage-temperature variations 有权
标题翻译：采用虚拟轨道方案的SRAM可以针对各种过程电压 - 温度变化进行稳定
公开(公告)号：US20060002223A1
公开(公告)日：2006-01-05
申请号：US11124787
申请日：2005-05-09
申请人： Tae-joong Song , Jae-seung Choi
发明人： Tae-joong Song , Jae-seung Choi
IPC分类号： G11C7/00
CPC分类号： G11C11/417
摘要： An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising a ground voltage by a threshold voltage of a transistor. Due to the use of PMOS and NMOS transistors of diode types connected between the power supply voltage and the virtual power supply voltage and the use of NMOS and PMOS transistors of diode types connected between the ground voltage and the virtual ground voltage, a virtual power supply voltage level and a virtual ground voltage level that are stable even against various PVT variations are provided, so that low-leakage current characteristics are stable.
摘要翻译： SRAM采用对过程电压 - 温度（PVT）变化稳定的虚拟轨道配置。 SRAM通过将晶体管的阈值电压降低电源电压和通过将接地电压提高到晶体管的阈值电压而获得的虚拟接地电压而向SRAM单元提供虚拟电源电压。由于使用连接在电源电压和虚拟电源电压之间的二极管类型的PMOS和NMOS晶体管，并且使用连接在地电压和虚拟接地电压之间的二极管类型的NMOS和PMOS晶体管，虚拟电源提供了即使对于各种PVT变化也是稳定的电压电平和虚拟接地电压电平，使得低漏电流特性是稳定的。

4. 发明申请

US20050122812A1 Semiconductor device having sense amplifier driver that controls enabling timing 有权
标题翻译：具有控制使能定时的读出放大器驱动器的半导体器件
公开(公告)号：US20050122812A1
公开(公告)日：2005-06-09
申请号：US10972855
申请日：2004-10-25
申请人： Tae-joong Song
发明人： Tae-joong Song
IPC分类号： G11C7/00 , G11C7/06 , G11C7/22
CPC分类号： G11C7/227 , G11C7/06 , G11C7/22
摘要： Provided are a semiconductor device having a sense amplifier driver and a method of generating a sense amplifier enable signal for enabling a sense amplifier. The semiconductor device includes a sense amplifier, which is comprised of a plurality of inverters which are connected in series, a power supply circuit, and a discharge circuit. In this semiconductor device, an enabling timing of the sense amplifier enable signal is controlled by delaying a time taken to evaluate a first dummy bit line from a power supply voltage to a ground voltage using parasitic capacitance between the first dummy bit line and a first complementary dummy bit line. The method of generating the sense amplifier enable signal is performed using the above-described sense amplifier.
摘要翻译：提供了一种具有读出放大器驱动器和产生用于使读出放大器启用的读出放大器使能信号的方法的半导体器件。半导体器件包括读出放大器，其由串联连接的多个反相器，电源电路和放电电路组成。在该半导体器件中，通过使用第一虚拟位线与第一互补的寄生电容之间的寄生电容，将从第一虚拟位线估计的时间从电源电压延迟至接地电压来控制读出放大器使能信号的使能定时虚拟位线。使用上述读出放大器来执行产生读出放大器使能信号的方法。

5. 发明授权

US06614710B2 Semiconductor memory device and data read method thereof 有权
公开(公告)号：US06614710B2
公开(公告)日：2003-09-02
申请号：US10037908
申请日：2001-11-09
申请人： Tae Joong Song , In Kyu Park
发明人： Tae Joong Song , In Kyu Park
IPC分类号： G11C800
CPC分类号： G11C8/16 , G11C7/1006 , G11C7/18
摘要： Disclosed is a semiconductor memory device and a data read method thereof. The semiconductor memory device comprises a memory cell array comprising a plurality of sub-arrays, said sub-arrays comprising a plurality of memory cells and repeaters, wherein each of said memory cells is connected to a corresponding pair of read word lines, a corresponding pair of read bitlines, a corresponding pair of write word lines, and a corresponding pair of write bitlines, and wherein each of said repeaters is connected to said corresponding pair of read bitlines of each said memory cell and a corresponding pair of common main read bitlines so as to transmit read data from said corresponding pair of read bitlines to said corresponding pair of common main read bitlines in response to an applied enable control signal.

6. 发明授权

US09748246B2 Semiconductor integrated circuits having contacts spaced apart from active regions 有权
公开(公告)号：US09748246B2
公开(公告)日：2017-08-29
申请号：US14877247
申请日：2015-10-07
申请人： Tae-Joong Song , Jung-Han Kim
发明人： Tae-Joong Song , Jung-Han Kim
IPC分类号： H01L27/092 , H01L27/02 , H03K3/356
CPC分类号： H01L27/0928 , H01L27/0207 , H01L27/092 , H03K3/356156
摘要： First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second direction. First and third gate structures, which are on the first active region and a first portion of the isolation layer between the first and second active regions, extend in the second direction and are spaced apart from each other in the first direction. Second and fourth gate structures, which are on the second active region and the first portion, extend in the second direction, are spaced apart from each other in the first direction, and face and are spaced apart from the first and third gate structures, respectively, in the second direction. First to fourth contacts are on portions of the first to fourth gate structures, respectively. The first and fourth contacts are connected, and the second and third contacts are connected.

7. 发明授权

US09627376B2 Semiconductor device with active fins separated by shallow and deep trench isolations and method for fabricating the same 有权
公开(公告)号：US09627376B2
公开(公告)日：2017-04-18
申请号：US14281224
申请日：2014-05-19
申请人： Tae-Joong Song , Jae-Ho Park , Kang-Hyun Baek
发明人： Tae-Joong Song , Jae-Ho Park , Kang-Hyun Baek
IPC分类号： H01L27/088 , H01L29/66 , H01L27/108 , H01L27/11 , H01L27/12
CPC分类号： H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L27/1108 , H01L27/1211 , H01L29/6681
摘要： A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.

8. 发明申请

US20140374828A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140374828A1
公开(公告)日：2014-12-25
申请号：US14281224
申请日：2014-05-19
申请人： Tae-Joong SONG , Jae-Ho PARK , Kang-Hyun BAEK
发明人： Tae-Joong SONG , Jae-Ho PARK , Kang-Hyun BAEK
IPC分类号： H01L27/088 , H01L27/11 , H01L27/12
CPC分类号： H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L27/1108 , H01L27/1211 , H01L29/6681
摘要： A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.
摘要翻译：半导体器件包括在衬底上彼此相邻的第一和第二存储单元区域。可以在第一和第二存储单元区域之间的边界处顺序层叠至少一个活性碱基和浅沟槽隔离。第一和第二活动翅片形成在浅沟槽隔离件的相应侧上，并且第一和第二活动翅片从活动底座突出。在活性基底的一侧上形成至少一个深沟槽隔离。

9. 发明授权

US07359266B2 Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same 有权
标题翻译：预充电电路和采用无效的弱预充电和均衡方案的方法和包括其的存储器件
公开(公告)号：US07359266B2
公开(公告)日：2008-04-15
申请号：US11706758
申请日：2007-02-15
申请人： Tae-joong Song , Young-keun Lee
发明人： Tae-joong Song , Young-keun Lee
IPC分类号： G11C7/00 , G11C11/00 , G11C5/06
CPC分类号： G11C11/413 , G11C7/12
摘要： Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.
摘要翻译：公开了采用无效弱预充电和均衡方案的预充电电路，包括其的存储装置和预充电方法。无效的弱预充电和均衡方案在感测和放大传送到所选位线和互补位线的存储器单元数据时评估所选位线和互补位线之间的电压差，同时平衡未选位线和互补位线。然后，该方案对所选择的位线和互补位线以及未选择的位线和互补位线进行预充电。这不需要对等于预定电压电平的非激活位线和互补位线的高预充电驱动能力，从而可以减小预充电电流和工作电流。

10. 发明授权

US07095665B2 Sense amplifier driver and semiconductor device comprising the same 有权
标题翻译：感测放大器驱动器和包括该驱动器的半导体器件
公开(公告)号：US07095665B2
公开(公告)日：2006-08-22
申请号：US11323855
申请日：2005-12-30
申请人： Tae-joong Song
发明人： Tae-joong Song
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C2207/065
摘要： Provided are a sense amplifier driver and a semiconductor device comprising the same. The sense amplifier driver outputting an enable signal for enabling a sense amplifier includes a first inverter, which receives an input signal and outputs an output signal swung between a ground voltage and a control voltage that is determined by the amount of an off-current flowing through at least one transistor existing in an inactive memory block, and a second inverter, which receives the output signal of the first inverter and delays and buffers the output signal of the first inverter by a period of time inversely proportional to a level of the control voltage. A point of time when the enable signal is activated varies according to a level of the control voltage. The semiconductor device detects data in response to the enable signal.
摘要翻译：提供了一种读出放大器驱动器和包括该驱动器的半导体器件。输出用于启用读出放大器的使能信号的读出放大器驱动器包括：第一反相器，其接收输入信号，并输出在接地电压和控制电压之间摆动的输出信号，该输出信号由流过的流过的电流量确定存在于不活动存储块中的至少一个晶体管和第二反相器，其接收第一反相器的输出信号，并延迟并缓冲第一反相器的输出信号与控制电压的电平成反比的时间段。使能信号激活的时间点根据控制电压的电平而变化。半导体器件响应于使能信号来检测数据。

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