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1. 发明授权

US09850227B2 Diaminopyrimidine derivatives and processes for the preparation thereof 有权
公开(公告)号：US09850227B2
公开(公告)日：2017-12-26
申请号：US14001475
申请日：2012-02-24
申请人： Hyun-Joo Lee , Dong-Hoon Kim , Tae-Kyun Kim , Young-Ae Yoon , Jae-Young Sim , Myung-Hun Cha , Eun-Jung Jung , Kyoung-Kyu Ahn , Tai-Au Lee
发明人： Hyun-Joo Lee , Dong-Hoon Kim , Tae-Kyun Kim , Young-Ae Yoon , Jae-Young Sim , Myung-Hun Cha , Eun-Jung Jung , Kyoung-Kyu Ahn , Tai-Au Lee
IPC分类号： A01N43/00 , A01N43/46 , A61K31/55 , C07D403/04 , C07D401/04 , C07D413/04 , C07D413/14 , C07D417/04
CPC分类号： C07D403/04 , C07D401/04 , C07D413/04 , C07D413/14 , C07D417/04
摘要： The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT4 receptor agonist, and therefore can be usefully applied for preventing or treating dysfunction in gastrointestinal motility, one of the gastrointestinal diseases, such as gastroesophageal reflux disease (GERD), constipation, irritable bowel syndrome (IBS), dyspepsia, post-operative ileus, delayed gastric emptying, gastroparesis, intestinal pseudo-obstruction, drug-induced delayed transit, or diabetic gastric atony.

2. 发明申请

US20130294133A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130294133A1
公开(公告)日：2013-11-07
申请号：US13596873
申请日：2012-08-28
申请人： Tae-Kyun KIM
发明人： Tae-Kyun KIM
IPC分类号： G11C5/06
CPC分类号： G11C7/1012 , G11C7/1048 , G11C11/4096
摘要： A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O circuit; and a path provider configured to select one of a direct path to a target internal circuit or an indirect path to the target internal circuit that is longer than the direct path in response to one or more path control signals and use the selected path when the data signal is transmitted between the I/O circuit and the plurality of internal circuits.
摘要翻译：半导体器件包括：I / O电路，被配置为输入/输出数据信号; 多个内部电路，被配置为向/从I / O电路发送和接收数据信号; 以及路径提供器，被配置为响应于一个或多个路径控制信号，选择目标内部电路的直接路径或到达目标内部电路的间接路径中的一条，所述间接路径比所述直接路径长，并且当所述数据信号在I / O电路和多个内部电路之间传输。

3. 发明授权

US08500246B2 Inkjet print head and manufacturing method thereof 有权
标题翻译：喷墨打印头及其制造方法
公开(公告)号：US08500246B2
公开(公告)日：2013-08-06
申请号：US12254094
申请日：2008-10-20
申请人： Sung Joon Park , Jin Wook Lee , Chang Shin Park , Tae Kyun Kim
发明人： Sung Joon Park , Jin Wook Lee , Chang Shin Park , Tae Kyun Kim
IPC分类号： B41J2/135
CPC分类号： B41J2/1404 , B41J2/1603 , B41J2/1623 , B41J2/1631 , Y10T156/10
摘要： An inkjet print head including a substrate and a first film member stacked on the substrate to form an ink path, and a manufacturing method thereof. The first film member includes a path-defining layer made of a photosensitive material and formed with the ink path, and an adhesive layer made of a photosensitive material and used to stably bond the path-defining layer to the substrate. With this configuration, the path-defining layer and the adhesive layer can be simultaneously stacked on the substrate and also, can be patterned simultaneously.
摘要翻译：一种喷墨打印头及其制造方法，所述喷墨打印头包括基板和堆叠在所述基板上以形成油墨通路的第一膜构件。第一膜构件包括由感光材料制成并形成有油墨通路的路径限定层和由感光材料制成的粘合层，用于将路径限定层稳定地粘合到基底。利用这种构造，路径限定层和粘合剂层可以同时堆叠在基板上，并且也可以同时被图案化。

4. 发明申请

US20120262210A1 CIRCUIT AND METHOD FOR DELAYING SIGNAL 有权
标题翻译：用于延迟信号的电路和方法
公开(公告)号：US20120262210A1
公开(公告)日：2012-10-18
申请号：US13332063
申请日：2011-12-20
申请人： Tae-Kyun KIM
发明人： Tae-Kyun KIM
IPC分类号： H03L7/24
CPC分类号： H03K5/135
摘要： A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.
摘要翻译：延迟电路包括：延迟单元，被配置为延迟参考输入信号并产生参考输出信号;以及存储单元，配置为响应于参考输入信号存储多个输入信号，并响应于参考输出输出所存储的信号信号。

5. 发明申请

US20120064704A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED BIT LINES 有权
标题翻译：用双绞线制造半导体器件的方法
公开(公告)号：US20120064704A1
公开(公告)日：2012-03-15
申请号：US13080415
申请日：2011-04-05
申请人： Tae-Kyun KIM
发明人： Tae-Kyun KIM
IPC分类号： H01L21/265 , H01L21/28 , H01L21/263
CPC分类号： H01L27/10885
摘要： A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.
摘要翻译：一种制造半导体器件的方法包括通过蚀刻衬底形成由沟槽隔离的多个体，形成掩埋位线间隙，填充每个沟槽的一部分，在掩埋位线的上表面上形成蚀刻停止层; 以及形成在蚀刻停止层上的与掩埋位线交叉的方向上延伸的字线。

6. 发明申请

US20120025878A1 SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 失效
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20120025878A1
公开(公告)日：2012-02-02
申请号：US13269511
申请日：2011-10-07
申请人： Tae-Kyun KIM
发明人： Tae-Kyun KIM
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.
摘要翻译：半导体器件包括多个同步时钟发生器，其被配置为通过混合具有相同频率的第一和第二源时钟信号的相位来产生多个同步时钟信号，第一时钟传输路径被配置为顺序地将第一源时钟信号施加到多个同步时钟生成器，通过向正向传送第一源时钟信号;第二时钟传输路径，被配置为通过沿第二源时钟信号向后传送来顺序地将第二源时钟信号施加到多个同步时钟发生器，以及多个数据输出单元，被配置为使多个数据与多个同步时钟信号同步并输出同步的多个数据。

7. 发明申请

US20110306192A1 METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME 有权
标题翻译：用于形成垂直晶体管的侵入区域的方法和使用其制造垂直晶体管的方法
公开(公告)号：US20110306192A1
公开(公告)日：2011-12-15
申请号：US13084220
申请日：2011-04-11
申请人： Yong Seok EUN , Tae Kyun KIM , Kyong Bong ROUH , Eun Shil PARK
发明人： Yong Seok EUN , Tae Kyun KIM , Kyong Bong ROUH , Eun Shil PARK
IPC分类号： H01L21/266
CPC分类号： H01L21/266 , H01L21/26513 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
摘要翻译：用于形成垂直晶体管的杂质区域的方法包括在半导体衬底内形成杂质离子结区域，并通过蚀刻形成杂质离子结区域的半导体衬底形成沟槽。执行蚀刻处理以去除杂质离子结区域的一部分，使得杂质离子接合区域的剩余部分暴露于沟槽的下侧壁以用作掩埋位线结区域。

8. 发明申请

US20110291727A1 DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME 有权
标题翻译：延迟电路及其驱动方法
公开(公告)号：US20110291727A1
公开(公告)日：2011-12-01
申请号：US12832470
申请日：2010-07-08
申请人： Tae-Kyun Kim
发明人： Tae-Kyun Kim
IPC分类号： H03K5/13
CPC分类号： H03H11/265 , H03K5/05 , H03K5/1534 , H03K2005/00293 , H03L7/06
摘要： A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.
摘要翻译：延迟电路包括：脉冲发生单元，被配置为产生响应于输入信号被激活并具有对应于延迟信息的脉冲宽度的脉冲信号;以及输出单元，被配置为响应于去激活而激活最终输出信号的脉冲信号。

9. 发明授权

US07932554B2 Semiconductor device having a modified recess channel gate and a method for fabricating the same 有权
标题翻译：具有修改的凹槽通道栅极的半导体器件及其制造方法
公开(公告)号：US07932554B2
公开(公告)日：2011-04-26
申请号：US11768731
申请日：2007-06-26
申请人： Tae Kyun Kim
发明人： Tae Kyun Kim
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/1037 , H01L29/66621
摘要： A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.
摘要翻译：具有修改的凹槽通道栅极的半导体器件包括由器件隔离层限定并且以规则间隔布置在半导体衬底上的有源区，每个有源区在长轴和短轴方向上延伸，在每个有源区中形成沟槽，所述沟槽包括在所述有源区的短轴方向上的阶梯状底面，以及形成在所述沟槽中的凹槽。

10. 发明申请

US20100258861A1 SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有凹槽的半导体器件及其制造方法
公开(公告)号：US20100258861A1
公开(公告)日：2010-10-14
申请号：US12614543
申请日：2009-11-09
申请人： Seung-Mi Lee , Yun-Hyuck Ji , Tae-Kyun Kim , Jin-Yul Lee
发明人： Seung-Mi Lee , Yun-Hyuck Ji , Tae-Kyun Kim , Jin-Yul Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66621 , H01L21/28114 , H01L21/28211 , H01L29/42368 , H01L29/66537 , H01L29/78
摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.
摘要翻译：半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度与阈值电压调整层相邻的区域。

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