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1. 发明授权

US08909998B2 Phase shift adjusting method and circuit 有权
标题翻译：相移调整方法和电路
公开(公告)号：US08909998B2
公开(公告)日：2014-12-09
申请号：US12946637
申请日：2010-11-15
申请人： Otto Schumacher , Martin Maier , Thomas Hein , Aaron John Nygren
发明人： Otto Schumacher , Martin Maier , Thomas Hein , Aaron John Nygren
IPC分类号： H03M13/33 , H04L7/02 , H04L7/04 , G01R31/317 , G06F11/07 , G06F1/10 , G06F11/18 , G01R31/3193 , G06F11/10 , G06F11/263 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/50 , H04L7/00
CPC分类号： H04L7/048 , G01R31/31725 , G01R31/31937 , G06F1/10 , G06F11/073 , G06F11/1004 , G06F11/18 , G06F11/186 , G06F11/263 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/023 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2207/2254 , H03M13/33 , H04L7/0008 , H04L7/0037 , H04L7/0091
摘要： Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.
摘要翻译：在发送设备处调整第一数据信号和时钟信号之间的第一相移的方法和系统。分别表示第一和第二测试数据的第一和第二测试信号被发送到接收设备。测试信号相对于时钟信号具有相应的相移。由发送的信号承载的第一和第二接收数据计算错误检测码。错误检测码从接收设备发送到发送设备。从错误检测码计算估计的第一接收数据，其中在第二接收数据与第二测试数据相同的假设下计算估计的第一接收数据。基于估计的第一接收数据和第一测试数据的比较来调整第一相移。

2. 发明授权

US08706958B2 Data mask encoding in data bit inversion scheme 有权
标题翻译：数据位反转方案中的数据掩码编码
公开(公告)号：US08706958B2
公开(公告)日：2014-04-22
申请号：US13223922
申请日：2011-09-01
申请人： Thomas Hein
发明人： Thomas Hein
IPC分类号： G06F12/00
CPC分类号： G11C7/1087 , G06F3/0619 , G06F13/4243 , G11C5/148 , G11C7/1009 , Y02D10/14 , Y02D10/151
摘要： Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.
摘要翻译：用于存储器电路的数据掩码和数据位反转编码和解码的装置，电路和方法。根据这些方法和电路，可以减少编码数据掩码信息和数据位反转信息所需的数据线/引脚的数量。在一个实施例中，用于一部分数据（例如数据字）的数据掩码和数据反转功能可以合并到公共引脚/数据线上。在其他实施例中，可以通过传输的数据字本身传送数据掩码指令，而不使用任何额外的引脚。根据这些实施例，引脚开销可以从每字节的两个引脚减少到每个字节一个引脚。

3. 发明授权

US08674999B2 Circuit 有权
标题翻译：电路
公开(公告)号：US08674999B2
公开(公告)日：2014-03-18
申请号：US13443011
申请日：2012-04-10
申请人： Thomas Hein
发明人： Thomas Hein
IPC分类号： G06F13/14
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093
摘要： An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
摘要翻译：电路的一个实施例包括一个输出缓冲器，一个数据接口至少位于一个传输数据的位置，该数据接口耦合到该输出缓冲器的一个输出端;一个命令/地址接口，耦合到输出缓冲器的输入端耦合到所述输出缓冲器的输入的存储器核心;以及控制器电路，被配置为将存储在所述输出缓冲器内的数据输出到所述数据接口，还被配置为使存储在所述存储器核心内的数据输出到所述输入，使得数据存储在输出缓冲器内，并进一步被配置为使得在命令/地址接口处接收到的数据提供给输出缓冲器的输入，使得数据被存储在输出缓冲器内。

4. 发明申请

US20130061006A1 DATA MASK ENCODING IN DATA BIT INVERSION SCHEME 有权
标题翻译：数据掩码编码数据位反转方案
公开(公告)号：US20130061006A1
公开(公告)日：2013-03-07
申请号：US13223922
申请日：2011-09-01
申请人： Thomas Hein
发明人： Thomas Hein
IPC分类号： G06F12/00
CPC分类号： G11C7/1087 , G06F3/0619 , G06F13/4243 , G11C5/148 , G11C7/1009 , Y02D10/14 , Y02D10/151
摘要： Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.
摘要翻译：用于存储器电路的数据掩码和数据位反转编码和解码的装置，电路和方法。根据这些方法和电路，可以减少编码数据掩码信息和数据位反转信息所需的数据线/引脚的数量。在一个实施例中，用于一部分数据（例如数据字）的数据掩码和数据反转功能可以合并到公共引脚/数据线上。在其他实施例中，可以通过传输的数据字本身传送数据掩码指令，而不使用任何额外的引脚。根据这些实施例，引脚开销可以从每字节的两个引脚减少到每个字节一个引脚。

5. 发明授权

US08392779B2 Interface voltage adjustment based on error detection 有权
标题翻译：基于错误检测的接口电压调整
公开(公告)号：US08392779B2
公开(公告)日：2013-03-05
申请号：US12109826
申请日：2008-04-25
申请人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
发明人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00
CPC分类号： G11C29/021 , G06F11/1004 , G11C7/1006 , G11C11/401 , G11C11/4074 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2029/0411 , H03M13/03
摘要： A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.
摘要翻译：调整接口电压的方法包括在存储器件和控制器之间传输数据，以及检测数据传输中是否发生错误。基于检测来调整存储器件和控制器中的至少一个的接口电压。

6. 发明申请

US20120198265A1 CIRCUIT 有权
标题翻译：电路
公开(公告)号：US20120198265A1
公开(公告)日：2012-08-02
申请号：US13443011
申请日：2012-04-10
申请人： Thomas Hein
发明人： Thomas Hein
IPC分类号： G06F1/12
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093
摘要： An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
摘要翻译：电路的一个实施例包括一个输出缓冲器，一个数据接口至少位于一个传输数据的位置，该数据接口耦合到该输出缓冲器的一个输出端;一个命令/地址接口，耦合到输出缓冲器的输入端耦合到所述输出缓冲器的输入的存储器核心;以及控制器电路，被配置为将存储在所述输出缓冲器内的数据输出到所述数据接口，还被配置为使存储在所述存储器核心内的数据输出到所述输入，使得数据存储在输出缓冲器内，并进一步被配置为使得在命令/地址接口处接收到的数据提供给输出缓冲器的输入，使得数据被存储在输出缓冲器内。

7. 发明申请

US20100077157A1 MULTI MASTER DRAM ARCHITECTURE 有权
标题翻译：多主体DRAM架构
公开(公告)号：US20100077157A1
公开(公告)日：2010-03-25
申请号：US12235063
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.
摘要翻译：本发明的实施例提供一种存储器件，其可以经由存储器件的相应端口被多个控制器或处理器核存取。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。在一些实施例中，存储器件可以是包括多个堆叠的存储器管芯的封装。

8. 发明授权

US07439761B2 Apparatus and method for controlling a driver strength 有权
标题翻译：用于控制驾驶员强度的装置和方法
公开(公告)号：US07439761B2
公开(公告)日：2008-10-21
申请号：US11457133
申请日：2006-07-12
申请人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
发明人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1069 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , H04L25/0278
摘要： Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating voltage with a frequency, wherein the signal line is terminated with a termination impedance, wherein the driver strength is changed depending on a changing of the frequency of the output signal.
摘要翻译：控制接口的信号线的驱动强度和终端阻抗的方法，其中所述驱动器将输出信号作为具有频率的交流电压发送，其中所述信号线以终端阻抗终止，其中所述驱动器强度改变取决于输出信号频率的变化。

9. 发明授权

US07428689B2 Data memory system and method for transferring data into a data memory 有权
标题翻译：用于将数据传送到数据存储器的数据存储器系统和方法
公开(公告)号：US07428689B2
公开(公告)日：2008-09-23
申请号：US11217081
申请日：2005-08-30
申请人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
发明人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
IPC分类号： G06F11/10
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译：提出了一种使用数据协议将数据传输到数据存储器中的方法。数据存储器是纠错码（ECC）存储器或非纠错码存储器。数据协议具有不同的帧。当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

10. 发明授权

US07411862B2 Control signal training 有权
标题翻译：控制信号训练
公开(公告)号：US07411862B2
公开(公告)日：2008-08-12
申请号：US11560293
申请日：2006-11-15
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.
摘要翻译：集成电路中的控制信号训练系统包括信号发送单元，信号发送单元输出控制信号和采样时钟信号，控制信号和采样时钟信号相对于彼此具有预定的时间相位;信号接收单元信号接收单元相对于采样时钟信号锁存控制信号，以及连接到读取单元和信号发送单元的评估单元，评估单元确定由信号发送单元输出的控制信号和控制信号的一致性由读取单元从信号接收单元读出，评估单元逐步调整控制信号与采样时钟信号之间的时间相位，直到由信号发送单元输出的控制信号和读取的控制信号的一致从信号接收单元输出读取单元由评估确定单位。

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