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    • 5. 发明申请
    • CLOCK GLITCH DETECTION CIRCUIT
    • 时钟检测电路
    • US20110317802A1
    • 2011-12-29
    • US13131349
    • 2009-01-05
    • Michael RohlederThomas KochVladimir LitovtchenkoThomas Luedeke
    • Michael RohlederThomas KochVladimir LitovtchenkoThomas Luedeke
    • H03K21/40H03K23/42
    • G06F1/04H03K5/1252
    • In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment. A comparator determines the difference between the first count and the second count, or determines whether the first count and the second count differ. The synchronous circuit may comprise the first circuit. A second circuit for detecting clock glitches in a clock signal is also provided. The second circuit is intended to be integrated in the synchronous circuit.
    • 在用于检测时钟信号中的时钟毛刺的第一电路中,主计数器由时钟信号计时,并存储主计数。 增量器将主计数递增一个增量。 从计数器由时钟信号计时,并存储从计数。 从计数相对于主计数延迟至少是时钟沿。 比较器确定主计数和从计数之间的差异是否至少为止。 在相关方面,同步电路包括用于将时钟信号从起始点发送到一个或多个其他点的时钟树,起始点和包括第一点和第二点的其他点。 第一计数器由第一点处的时钟信号计时,并记忆第一个计数。 第一增量器将第一计数递增一个增量。 第二计数器由第二点处的时钟信号计时,并存储第二计数。 第二个递增器将第二个计数递增一个增量。 比较器确定第一计数和第二计数之间的差,或者确定第一计数和第二计数是否不同。 同步电路可以包括第一电路。 还提供了用于检测时钟信号中的时钟毛刺的第二电路。 第二个电路旨在集成在同步电路中。