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1. 发明授权

US10250237B2 Electronic latch circuit and a generic multi-phase signal generator 有权
公开(公告)号：US10250237B2
公开(公告)日：2019-04-02
申请号：US15517574
申请日：2015-05-04
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Reza Bagger
IPC分类号： H03K3/356 , H03K3/3562 , H03K21/10 , H03K23/42 , H03K19/20 , H04B1/40 , H03K5/15 , H03K3/37 , H03K23/48
摘要： An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

2. 发明授权

US09685966B2 Fractional dividing module and related calibration method 有权
公开(公告)号：US09685966B2
公开(公告)日：2017-06-20
申请号：US14922203
申请日：2015-10-26
申请人： MEDIATEK INC.
发明人： Pang-Ning Chen , Yu-Li Hsueh , Jian-Yu Ding
IPC分类号： H03L7/197 , H03L7/081 , H03K21/02 , H03K23/42
CPC分类号： H03L7/1976 , H03K21/023 , H03K23/42 , H03L7/081 , H03L7/1974
摘要： A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.

3. 发明申请

US20160285458A1 LOW PHASE NOISE FREQUENCY DIVIDER 有权
标题翻译：低相位噪声分频器
公开(公告)号：US20160285458A1
公开(公告)日：2016-09-29
申请号：US14666060
申请日：2015-03-23
申请人： Peregrine Semiconductor Corporation
发明人： Gary Chunshien Wu
IPC分类号： H03K23/42 , H03L7/08
CPC分类号： H03K23/42 , H03L7/193 , H03L7/1976
摘要： A low phase noise frequency divider suitable for use in phase locked loops (PLL) and frequency synthesizers, particular in a fractional-N PLL system having an N frequency divider with a main (M) counter and an auxiliary (A) counter. In some user selectable cases, the count value CM for the M counter is fixed and only the count value CA for the A counter is varied. Having a fixed CM value results in lower phase noise in most cases. For cases where it is not possible to vary CM, then CM is allowed to vary in a conventional manner to retain a full range of functionality.
摘要翻译：适用于锁相环（PLL）和频率合成器的低相位噪声分频器，特别是在具有N（M）计数器和辅助（A）计数器的N分频器的分数N PLL系统中。在一些用户选择的情况下，M计数器的计数值CM是固定的，并且仅A计数器的计数值CA是变化的。在大多数情况下，具有固定的CM值可导致较低的相位噪声。对于不可能改变CM的情况，允许CM以常规方式变化以保持全部功能。

4. 发明授权

US09379714B1 Circuits and methods of TAF-DPS vernier caliper for time-of-flight measurement 有权
标题翻译： TAF-DPS游标卡尺的电路和方法，用于飞行时间测量
公开(公告)号：US09379714B1
公开(公告)日：2016-06-28
申请号：US14726666
申请日：2015-06-01
申请人： Liming Xiu
发明人： Liming Xiu
IPC分类号： G04F10/00 , H03K21/02 , G01S7/486 , G01S7/526 , G01S7/285 , H03L7/191 , H03K23/42
CPC分类号： H03K21/026 , G01S7/2806 , G01S7/4865 , G01S7/523 , G01S13/103 , G01S13/30 , G01S15/101 , G01S15/108 , G04F10/005 , H03K23/42 , H03L7/0995 , H03L7/18
摘要： Circuits for measuring TOF between two electrical signals comprises 1) a slow TAF-DPS clock signal generator for generating a slow clock signal, a fast TAF-DPS clock signal generator for generating a fast clock signal, said slow TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer, said fast TAF-DPS clock signal generator comprises a gated ring oscillator and a TAF-DPS frequency synthesizer; 2) a phase detector for receiving said slow and fast clock signals and detecting point-of-coincidence between said slow and fast clock signals; 3) a first digital counter driven by said slow clock signal for storing the number of slow clock cycles and a second digital counter driven by said fast clock signal for storing the number of fast clock cycles; 4) a calibrator for calibrating said gate ring oscillators; 5) a calculation block for calculating TOF measurement result. Methods of using a slow TAF-DPS clock generator and a fast TAF-DPS clock generator for measuring TOF between two electrical signals are also disclosed.
摘要翻译：用于测量两个电信号之间的TOF的电路包括1）用于产生慢时钟信号的慢TAF-DPS时钟信号发生器，用于产生快时钟信号的快速TAF-DPS时钟信号发生器，所述慢TAF-DPS时钟信号发生器包括门控环形振荡器和TAF-DPS频率合成器，所述快速TAF-DPS时钟信号发生器包括门控环形振荡器和TAF-DPS频率合成器; 2）相位检测器，用于接收所述慢和快时钟信号并检测所述慢速和快速时钟信号之间的重合点; 3）由所述慢时钟信号驱动的用于存储慢时钟周期数的第一数字计数器和由所述快速时钟信号驱动的用于存储快速时钟周期数的第二数字计数器; 4）校准器，用于校准所述门环振荡器; 5）用于计算TOF测量结果的计算块。还公开了使用慢TAF-DPS时钟发生器和用于测量两个电信号之间的TOF的快速TAF-DPS时钟发生器的方法。

5. 发明授权

US09094017B2 Control circuitry 有权
标题翻译：控制电路
公开(公告)号：US09094017B2
公开(公告)日：2015-07-28
申请号：US13686110
申请日：2012-11-27
申请人： Sequans Communications, Ltd.
发明人： Jackson Harvey , Peter Martin
IPC分类号： H03L7/00 , H03K21/40 , H03K23/42
CPC分类号： H03K21/40 , H03K23/425 , H03L7/00
摘要： An arrangement is described in which phase parity or phase opposition between two signals can be determined, and if necessary remedial action may be taken.
摘要翻译：描述了可以确定两个信号之间的相位奇偶校验或相位相反的布置，并且如果需要，可以采取补救措施。

6. 发明授权

US4587664A High speed frequency divider dividing pulse by a number obtained by dividing an odd number by two 失效
标题翻译：高速分频器将通过将奇数除以2而获得的数字进行分频
公开(公告)号：US4587664A
公开(公告)日：1986-05-06
申请号：US653109
申请日：1984-09-21
申请人： Norihiko Iida
发明人： Norihiko Iida
IPC分类号： H03K23/66 , H03K23/68 , H03K23/42 , H03K23/48 , H03K23/52
CPC分类号： H03K23/667 , H03K23/68
摘要： An 8.5 divider comprises a first and second 1/2 dividers to produce output pulses having phases different from each other by 90.degree., a first logic gate producing output pulses having a repetition frequency of a half of the input pulses, a third and fourth 1/2 dividers connected in series and dividing twice the output pulses of the first logic gate by two, a fifth 1/2 divider receiving the output of the fourth 1/2 divider, a second logic gate detecting the simultaneous presence of the outputs of the second, third and fifth 1/2 dividers to invert the phase of the output pulses of the first 1/2 divider and a third logic gate detecting the simultaneous presence of the outputs of the first and third 1/2 dividers and the inverted output of the fifth 1/2 divider.
摘要翻译： 8.5分频器包括第一和第二1/2分频器以产生具有彼此相差90°的相位的输出脉冲，第一逻辑门产生具有输入脉冲的一半重复频率的输出脉冲，第三和第四1 / 2分频器串联连接，将第一逻辑门的输出脉冲的两倍除以2，第五1/2分频器接收第四1/2分频器的输出;第二逻辑门检测同时存在的第二逻辑门的输出第二，第三和第五1/2分频器，以反转第一1/2分频器的输出脉冲的相位和第三逻辑门，其检测第一和第三1/2分频器的输出的同时存在以及反相输出第五分1/2分。

7. 发明授权

US4193037A Frequency divider circuit with selectable integer/non-integer division 失效
标题翻译：分频电路，可选择整数/非整数除法
公开(公告)号：US4193037A
公开(公告)日：1980-03-11
申请号：US888441
申请日：1978-03-20
申请人： Shikun Kyu
发明人： Shikun Kyu
IPC分类号： H03K23/54 , H03K23/42 , H03K23/66 , H03K23/68 , H03K21/36
CPC分类号： H03K23/68 , H03K23/425 , H03K23/665
摘要： A divide circuit is provided for dividing an input signal of frequency N by the quantity M+0.5, where N is any positive number and M is an integer. In one embodiment a clock signal operating at a frequency of 3.5 megahertz is divided by 3.5, yielding an output signal of 1 megahertz. Additional logic means may be provided responsive to a control signal for dividing the input signal by the quantity M+1 for a given state of the control signal.
摘要翻译：分频电路用于将频率N的输入信号除以M + 0.5，其中N是任何正数，M是整数。在一个实施例中，以3.5兆赫兹频率工作的时钟信号除以3.5，产生1兆赫兹的输出信号。可以响应于控制信号来提供附加逻辑装置，用于将控制信号的给定状态的输入信号除以量M + 1。

8. 发明授权

US3956880A Solid state wristwatch with charge coupled divider 失效
标题翻译：固态手表带电荷耦合分压器
公开(公告)号：US3956880A
公开(公告)日：1976-05-18
申请号：US407583
申请日：1973-10-18
申请人： Arthur H. O'Connor
发明人： Arthur H. O'Connor
IPC分类号： G04G3/02 , G11C19/18 , H03K3/354 , H03K23/42 , G04C3/00 , G04B19/30 , H03F3/02 , H03K21/02
CPC分类号： H03K23/425 , G04G3/02 , G11C19/186 , H03K3/3545
摘要： This invention relates to a solid state timepiece and more particularly to an electronic watch which employs no moving parts. In the present invention a frequency standard in the form of a crystal oscillator acts through a solid state electronic circuit divider and display actuator to power in timed sequence the light-emitting diodes of an electro-optic display. Low cost, low power consumption and small size and weight are achieved through the use of a charge coupled binary divider chain.
摘要翻译：本发明涉及一种固态钟表，更具体地涉及一种不使用移动部件的电子手表。在本发明中，晶体振荡器形式的频率标准通过固态电子分路器和显示致动器来按时间顺序驱动电光显示器的发光二极管。低成本，低功耗，小尺寸和重量通过使用电荷耦合二进制分频器链来实现。

9. 发明授权

US11362666B2 Low-jitter frequency division clock clock circuit 有权
公开(公告)号：US11362666B2
公开(公告)日：2022-06-14
申请号：US17264298
申请日：2018-12-13
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
发明人： Tao Liu , Jian'an Wang , Yuxin Wang , Guangbing Chen , Dongbing Fu , Ruzhang Li , Shengdong Hu , Zhengping Zhang , Jun Luo , Daiguo Xu , Minming Deng , Yan Wang
IPC分类号： H03K23/00 , H03K23/44 , H03K3/356 , H03K5/15 , H03K23/42 , H03K23/50 , H03K23/52 , H03K23/66
摘要： The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

10. 发明授权

US10447251B2 Power efficient high speed latch circuits and systems 有权
公开(公告)号：US10447251B2
公开(公告)日：2019-10-15
申请号：US15522052
申请日：2015-12-02
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Reza Bagger
IPC分类号： H03K3/356 , H03K3/3562 , H03K21/10 , H03K23/42 , H03K19/20 , H04B1/40 , H03K5/15 , H03K3/37 , H03K23/48
摘要： The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.

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