专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09176876B2 Selective cache-to-cache lateral castouts 有权
公开(公告)号：US09176876B2
公开(公告)日：2015-11-03
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

2. 发明申请

US20080010555A1 Method and Apparatus for Measuring the Cost of a Pipeline Event and for Displaying Images Which Permit the Visualization orf Said Cost 审中-公开
标题翻译：用于测量管道事件的成本和显示允许可视化或所述成本的图像的方法和装置
公开(公告)号：US20080010555A1
公开(公告)日：2008-01-10
申请号：US11424696
申请日：2006-06-16
申请人： Phillip Emma , Alian Hartstein , Daniel N. Lynch , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Phillip Emma , Alian Hartstein , Daniel N. Lynch , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F11/00
CPC分类号： G06F11/3423 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A hardware monitor is used to monitor the sequence of instructions executed during a miss cluster. The monitor groups each cache miss into a miss cluster, and the miss penalty associated with each cluster is determined by identifying a set of instructions that were executed during the miss cluster. The finite cache running time is then calculated for the set of instructions that occurred during the miss cluster. Additionally, an infinite cache running time is determined for the same set of instructions that occurred during the miss cluster, where the infinite cache running time is the time needed to execute this set of instructions in the absence of any miss. The cost of the miss cluster is then calculated by measuring the difference between the finite cache running time and the infinite cache running time.
摘要翻译：硬件监视器用于监视在小组群集期间执行的指令序列。监视器将每个高速缓存未命中组合成一个未命中集群，并且通过识别一组在缺少集群期间执行的指令来确定与每个集群相关联的丢失代价。然后针对在缺少集群期间发生的指令集计算有限缓存运行时间。另外，对于在缺少集群期间发生的相同指令集，确定无限缓存运行时间，其中无限高速缓存运行时间是在没有任何缺失的情况下执行该组指令所需的时间。然后，通过测量有限缓存运行时间和无限缓存运行时间之间的差异来计算小数簇的成本。

3. 发明授权

US5353421A Multi-prediction branch prediction mechanism 失效
标题翻译：多预测分支预测机制
公开(公告)号：US5353421A
公开(公告)日：1994-10-04
申请号：US91416
申请日：1993-07-13
申请人： Philip G. Emma , Joshua W. Knight , James H. Po merene , Thomas R. Puzak , Rudolph N. Rechtschaffen , James R. Robinson
发明人： Philip G. Emma , Joshua W. Knight , James H. Po merene , Thomas R. Puzak , Rudolph N. Rechtschaffen , James R. Robinson
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A multi-prediction branch prediction mechanism predicts each conditional branch at least twice, first during the instruction-fetch phase of the pipeline and then again during the decode phase of the pipeline. The mechanism uses at least two different branch prediction mechanisms, each a separate and independent mechanism from the other. A set of rules are used to resolve those instances as to when the predictions differ.
摘要翻译：多预测分支预测机制首先在流水线的指令获取阶段期间至少预测每个条件分支，然后再次在流水线的解码阶段期间。该机制使用至少两个不同的分支预测机制，每个分离机制与另一个独立的机制相互独立。使用一组规则来解决这些实例关于预测不同的情况。

4. 发明授权

US08521999B2 Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history 有权
标题翻译：执行touchBHT指令，预先获取信息到具有历史记录的分支预测机制
公开(公告)号：US08521999B2
公开(公告)日：2013-08-27
申请号：US12721933
申请日：2010-03-11
申请人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/30145 , G06F9/3846 , G06F9/3848
摘要： A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
摘要翻译：一种方法，包括接收分支指令，解码分支地址和分支指令，执行与分支地址相关联的分支动作，确定是否采用与分支动作相关联的分支，以及保存分支指令的标识符和指示符响应于确定与分支动作相关联的分支被采取，分支动作被采取在预取历史表中。

5. 发明申请

US20110161780A1 METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE 有权
标题翻译：提供改进存储缓存的方法和系统
公开(公告)号：US20110161780A1
公开(公告)日：2011-06-30
申请号：US13041248
申请日：2011-03-04
申请人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F12/0802 , G06F11/1064 , G06F11/1666
摘要： A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.
摘要翻译：硬化的存储缓存系统包括具有存储有校验位的第一行的行的存储高速缓存，其中校验位包括字节奇偶校验位，以及保存最近存储的副本的辅助存储高速缓存（ASOC）到存储缓存中的行。 ASOC包括比存储缓存更少的行，ASOC的每一行都具有与检查位一起存储的第一行。

6. 发明申请

US20110161589A1 SELECTIVE CACHE-TO-CACHE LATERAL CASTOUTS 有权
标题翻译：选择性高速缓存行驶路线
公开(公告)号：US20110161589A1
公开(公告)日：2011-06-30
申请号：US12650018
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
摘要翻译：数据处理系统包括第一和第二处理单元和系统存储器。第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO）基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

7. 发明授权

US07441110B1 Prefetching using future branch path information derived from branch prediction 失效
标题翻译：使用从分支预测得到的未来分支路径信息进行预取
公开(公告)号：US07441110B1
公开(公告)日：2008-10-21
申请号：US09458883
申请日：1999-12-10
申请人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden
发明人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3844
摘要： A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.
摘要翻译：描述了一种机制，其预测在指令的解码周期期间预取指令的有用性。被预测为有用的预取指令（预取有用数据）被发送到处理器的执行单元用于执行，而被预测为无用的指令被丢弃。使用包含在分支历史机制中的分支预测掩模来执行关于预取指令的有用性的预测。将该掩码与包含在预取指令中的信息进行比较，该预取指令记录预取指令和数据的实际使用之间的分支路径。可以使用这种机制来预取指令和数据。

8. 发明授权

US4774654A Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory 失效
标题翻译：根据代替低速存储器中的位的状态，将子块从低速存储器预取到存储器层级的高速存储器的装置和方法
公开(公告)号：US4774654A
公开(公告)日：1988-09-27
申请号：US685527
申请日：1984-12-24
申请人： James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Kimming So
发明人： James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Kimming So
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6024
摘要： A prefetching mechanism for a memory hierarchy which includes at least two levels of storage, with L1 being a high-speed low-capacity memory, and L2 being a low-speed high-capacity memory, with the units of L2 and L1 being blocks and sub-blocks respectively, with each block containing several sub-blocks in consecutive addresses. Each sub-block is provided an additional bit, called a r-bit, which indicates that the sub-block has been previously stored in L1 when the bit is 1, and has not been previously stored in L1 when the bit is 0. Initially when a block is loaded into L2 each of the r-bits in the sub-block are set to 0. When a sub-block is transferred from L1 to L2, its r-bit is then set to 1 in the L2 block, to indicate its previous storage in L1. When the CPU references a given sub-block which is not present in L1, and has to be fetched from L2 to L1, the remaining sub-blocks in this block having r-bits set to 1 are prefetched to L1. This prefetching of the other sub-blocks having r-bits set to 1 results in a more efficient utilization of the L1 storage capacity and results in a highter hit ratio.
摘要翻译：一种用于存储器层级的预取机制，其包括至少两个级别的存储，L1是高速低容量存储器，L2是低速大容量存储器，L2和L1的单位是块，子块，每个块包含连续地址中的几个子块。每个子块被提供一个称为r位的附加位，该位指示当该位为1时该子块已经预先存储在L1中，并且当该位为0时，该块尚未预先存储在L1中。最初当块被加载到L2中时，子块中的每个r位被设置为0.当子块从L1传送到L2时，其r位在L2块中被设置为1，到表示其以前在L1中的存储。当CPU参考L1中不存在并且必须从L2取出的给定子块时，将具有设置为1的r位的该块中剩余的子块预取为L1。将r位设置为1的其他子块的预取导致L1存储容量的更有效的利用并导致更高的命中率。

9. 发明授权

US10338923B2 Branch prediction path wrong guess instruction 有权
公开(公告)号：US10338923B2
公开(公告)日：2019-07-02
申请号：US12435631
申请日：2009-05-05
申请人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
发明人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0862 , G06F8/41
摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

10. 发明申请

US20100287358A1 Branch Prediction Path Instruction 审中-公开
标题翻译：分支预测路径指令
公开(公告)号：US20100287358A1
公开(公告)日：2010-11-11
申请号：US12435631
申请日：2009-05-05
申请人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
发明人： Philip G. Emma , Allan M. Hartstein , Keith N. Langston , Brian R. Prasky , Thomas R. Puzak , Charles F. Webb
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30047 , G06F8/4442 , G06F9/3005 , G06F9/30054 , G06F9/30058 , G06F9/30076 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/383 , G06F9/3842 , G06F9/3844 , G06F9/3846 , G06F9/3848 , G06F12/0862 , G06F2212/6028
摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.
摘要翻译：一种分支预测方法，所述方法包括：接收具有分支错误猜测指令地址的分支错误猜测指令和包括操作码和分支目标地址的数据，确定分支错误猜测指令是否由分支预测机制预测，发送分支对执行单元的错误猜测指令响应于确定分支错误猜测指令由分支预测机制预测，以及在分支目标地址处的接收和解码指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式