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    • 3. 发明授权
    • Plan execution control apparatus, plan execution control method, and plan execution control program
    • 计划执行控制装置,计划执行控制方法以及计划执行控制程序
    • US08650060B2
    • 2014-02-11
    • US12466296
    • 2009-05-14
    • Tohru WatanabeHiroyuki Hori
    • Tohru WatanabeHiroyuki Hori
    • G06Q10/00
    • G06Q10/06G06Q10/0631G06Q10/0639
    • The invention provides a plan execution control apparatus, a plan execution control method and a plan execution control program capable of giving instructions for sensitively and efficiently maintaining even installations located in a wide range. The plan execution control apparatus includes a linkage reliability calculating section for calculating a target reliability of a single or a plurality of mutually related installations, a damaged state transition control section that provides a damaged state transition structure of the installations, a maintenance time limit calculating section for calculating a time limit related to the maintenance work to meet the target level of reliability of each key point and section, the constraint control section for recognizing and recording the constraints related to traveling of maintenance personnel, the traveling workload and the acceptable workload, and the itinerary maintenance determining section for calculating the itinerary schedule indicating the assignment to the object to be maintained.
    • 本发明提供一种计划执行控制装置,计划执行控制方法和计划执行控制程序,其能够给位于大范围内的均匀安装的敏感且有效地保持指令。 计划执行控制装置包括:联动可靠性计算部,其计算单个或多个相互关联的装置的目标可靠性;提供设备的损坏状态转移结构的损坏状态转移控制部;维护时间限制计算部 为了计算与维护工作相关的时间限制以满足每个关键点和部分的目标可靠性水平,用于识别和记录与维护人员的旅行有关的约束的约束控制部分,旅行工作量和可接受的工作量,以及 行程维护确定部分,用于计算指示对待维护的对象的分配的行程计划。
    • 8. 发明授权
    • Image signal processor with reduced power consumption
    • 图像信号处理器功耗降低
    • US07173664B2
    • 2007-02-06
    • US10208588
    • 2002-07-30
    • Tohru WatanabeTakashi TanimotoTatsuya Takahashi
    • Tohru WatanabeTakashi TanimotoTatsuya Takahashi
    • H04N5/225
    • H04N5/23241H04N5/335
    • An image signal processor for reducing power consumption. The image signal processor is connected between a solid-state imaging device, which generates a first image signal, and an external device, and includes first and second regulators, a switch circuit, a signal processing circuit, and an output circuit. The first regulator generates a first voltage that is in accordance with an output level of the solid-state imaging device. The second regulator generates a second voltage that is in accordance with an input level of the external device. The switch circuit supplies the power supply voltage or the second voltage to the output circuit in accordance with the operating state of the imaging external device. The signal processing circuit operates with the first voltage and generates a second image signal. The output circuit provides the second image signal to the external device.
    • 一种用于降低功耗的图像信号处理器。 图像信号处理器连接在产生第一图像信号的固态成像装置和外部装置之间,并且包括第一和第二调节器,开关电路,信号处理电路和输出电路。 第一调节器产生与固态成像装置的输出电平相一致的第一电压。 第二调节器产生与外部设备的输入电平相对应的第二电压。 开关电路根据成像外部设备的操作状态将电源电压或第二电压提供给输出电路。 信号处理电路以第一电压工作并产生第二图像信号。 输出电路将第二图像信号提供给外部设备。
    • 9. 发明申请
    • Image Signal Processor and Deficient Pixel Detection Method
    • 图像信号处理器和缺陷像素检测方法
    • US20060233431A1
    • 2006-10-19
    • US11426754
    • 2006-06-27
    • Tohru Watanabe
    • Tohru Watanabe
    • H04N17/02G06K9/00
    • G09G3/006G06T5/005G06T5/20G06T7/0002G09G2330/10H01L27/14806H04N5/21H04N5/367H04N5/3675
    • A deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats the determination of a deficient pixel a number of times based on the address information stored in the position memory circuit, and determines address information of a deficient pixel from the continuity of the determination results. A deficiency registering circuit registers the determined address information in the position memory circuit. A deficiency correction circuit corrects the image signal of the deficient pixel according to the registered address information of the deficient pixel.
    • 不足候选检测电路通过将目标像素的图像信号与周边像素的图像信号进行比较来检测缺陷像素候选,并且将不良像素候选的地址信息存储在位置存储电路中。 缺陷判定电路基于存储在位置存储电路中的地址信息重复不良像素的判定次数,根据判定结果的连续性来判定缺陷像素的地址信息。 缺陷登记电路将确定的地址信息登记在位置存储电路中。 缺陷校正电路根据缺陷像素的注册地址信息校正缺陷像素的图像信号。