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1. 发明申请

US20090089494A1 Memory control apparatus, memory control method, and computer program 有权
标题翻译：存储器控制装置，存储器控制方法和计算机程序
公开(公告)号：US20090089494A1
公开(公告)日：2009-04-02
申请号：US12232048
申请日：2008-09-10
申请人： Tomohiro Koganezawa
发明人： Tomohiro Koganezawa
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G06F13/1636 , G11C11/40611 , G11C2211/4061 , Y02D10/14
摘要： Disclosed herein is a memory control apparatus including a plurality of memory control sections, each of which has connected thereto one or more memories that require periodic refresh and is configured to perform data write, data read, and refresh operations on the one or more memories. The memory control sections issue, to each of the one or more memories, refresh commands at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.
摘要翻译：这里公开了一种包括多个存储器控制部分的存储器控制装置，每个存储器控制部分已经连接到需要周期性刷新的一个或多个存储器，并被配置为对一个或多个存储器执行数据写入，数据读取和刷新操作。存储器控制部分以最佳间隔和任意定时向每个一个或多个存储器发出刷新命令，使得消耗高功率的命令彼此不冲突。

2. 发明授权

US08068150B2 Memory access control apparatus and image pickup apparatus 失效
标题翻译：存储器访问控制装置和图像拾取装置
公开(公告)号：US08068150B2
公开(公告)日：2011-11-29
申请号：US12487124
申请日：2009-06-18
申请人： Tomohiro Koganezawa , Takeshi Shimoyama , Kingo Koyama , Takuji Himeno
发明人： Tomohiro Koganezawa , Takeshi Shimoyama , Kingo Koyama , Takuji Himeno
IPC分类号： H04N5/225
CPC分类号： H04N5/232 , G06F13/1689 , H04N5/23245
摘要： A memory access control apparatus includes a memory controller controlling a memory adopting a DDR format; a DDR-PHY adjusting the timing of an interface signal between the memory controller and the memory; a DDR-PHY controller controlling the DDR-PHY; and a clock controller controlling the frequency of a clock signal. A first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller, a second request signal for resetting the DDR-PHY is supplied to the DDR-PHY controller, a third request signal for changing the clock frequency is supplied to the clock controller, a fourth request signal for setting a parameter for the DDR-PHY is supplied to the DDR-PHY controller, and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller in order to change the clock frequency of the memory.
摘要翻译：存储器访问控制装置包括控制采用DDR格式的存储器的存储器控制器; DDR-PHY调整存储器控制器和存储器之间的接口信号的定时; 控制DDR-PHY的DDR-PHY控制器; 以及控制时钟信号的频率的时钟控制器。用于在自刷新模式下控制存储器的操作的第一请求信号被提供给存储器控制器，用于复位DDR-PHY的第二请求信号被提供给DDR-PHY控制器，第三请求信号用于改变将时钟频率提供给时钟控制器，将用于设置DDR-PHY的参数的第四请求信号提供给DDR-PHY控制器，并且用于在自刷新模式下取消存储器的操作的第五请求信号是提供给存储器控制器以便改变存储器的时钟频率。

3. 发明授权

US08543777B2 Memory control apparatus, memory control method, and computer program with refresh commands at optimum intervals 有权
标题翻译：存储器控制装置，存储器控制方法和具有最佳间隔刷新命令的计算机程序
公开(公告)号：US08543777B2
公开(公告)日：2013-09-24
申请号：US12232048
申请日：2008-09-10
申请人： Tomohiro Koganezawa
发明人： Tomohiro Koganezawa
IPC分类号： G06F13/00
CPC分类号： G11C11/406 , G06F13/1636 , G11C11/40611 , G11C2211/4061 , Y02D10/14
摘要： A memory control apparatus includes memory control sections that read and write data from and to the DRAMs. The memory control sections periodically refresh the DRAMs. The refresh rate is set to avoid the conflict of the refresh operations as well as read and write operations that consume high power. A memory control method includes connecting memories in a memory control section where the memories perform periodic refresh and perform data write, data read, and refresh operations. Refresh commands are issued at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.
摘要翻译：存储器控制装置包括从DRAM读取和写入数据的存储器控制部分。存储器控制部分周期性地刷新DRAM。刷新率被设置为避免刷新操作的冲突以及消耗高功率的读写操作。存储器控制方法包括在存储器控制部分中连接存储器，其中存储器执行周期性刷新并执行数据写入，数据读取和刷新操作。刷新命令以最佳间隔和任意时序发出，使得消耗高功率的命令不会相互冲突。

4. 发明申请

US20100007770A1 MEMORY ACCESS CONTROL APPARATUS AND IMAGE PICKUP APPARATUS 失效
标题翻译：存储器访问控制装置和图像拾取装置
公开(公告)号：US20100007770A1
公开(公告)日：2010-01-14
申请号：US12487124
申请日：2009-06-18
申请人： Tomohiro KOGANEZAWA , Takeshi Shimoyama , Kingo Koyama , Takuji Himeno
发明人： Tomohiro KOGANEZAWA , Takeshi Shimoyama , Kingo Koyama , Takuji Himeno
IPC分类号： H04N5/225 , G06F12/02
CPC分类号： H04N5/232 , G06F13/1689 , H04N5/23245
摘要： A memory access control apparatus includes a memory controller controlling a memory adopting a DDR format; a DDR-PHY adjusting the timing of an interface signal between the memory controller and the memory; a DDR-PHY controller controlling the DDR-PHY; and a clock controller controlling the frequency of a clock signal. A first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller, a second request signal for resetting the DDR-PHY is supplied to the DDR-PHY controller, a third request signal for changing the clock frequency is supplied to the clock controller, a fourth request signal for setting a parameter for the DDR-PHY is supplied to the DDR-PHY controller, and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller in order to change the clock frequency of the memory.
摘要翻译：存储器访问控制装置包括控制采用DDR格式的存储器的存储器控制器; DDR-PHY调整存储器控制器和存储器之间的接口信号的定时; 控制DDR-PHY的DDR-PHY控制器; 以及控制时钟信号的频率的时钟控制器。用于在自刷新模式下控制存储器的操作的第一请求信号被提供给存储器控制器，用于复位DDR-PHY的第二请求信号被提供给DDR-PHY控制器，第三请求信号用于改变将时钟频率提供给时钟控制器，将用于设置DDR-PHY的参数的第四请求信号提供给DDR-PHY控制器，并且用于在自刷新模式下取消存储器的操作的第五请求信号是提供给存储器控制器以便改变存储器的时钟频率。

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