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1. 发明授权

US09189545B2 Content summarizing apparatus and content summarizing displaying apparatus 有权
标题翻译：内容总结装置和内容总结显示装置
公开(公告)号：US09189545B2
公开(公告)日：2015-11-17
申请号：US13071580
申请日：2011-03-25
申请人： Tomoyuki Shibata
发明人： Tomoyuki Shibata
IPC分类号： G06F3/00 , G06F17/30 , H04N21/234 , H04N21/8549
CPC分类号： G06F17/30793 , G06F17/30837 , H04N21/23418 , H04N21/8549
摘要： According to one embodiment, a content summarizing apparatus includes a selection unit, a record unit, and a storage unit. The selection unit selects at least one image from input content in accordance with at least one selection criterion and at least one parameter corresponding to the at least one selection criterion, and to produce a summary. The record unit cause the storage unit to store a summary record information item that includes the at least one selection criterion and the at least one parameter used by the selection unit. The storage unit stores the summary record information item whenever the summary of the input content is produced. The selection unit acquires past summary record information items from the storage unit, and produces the summary using the at least one selection criterion and the at least one parameter that fails to be included in the past summary record information items.
摘要翻译：根据一个实施例，内容总结装置包括选择单元，记录单元和存储单元。选择单元根据至少一个选择标准和与至少一个选择标准对应的至少一个参数从输入内容中选择至少一个图像，并且产生一个总结。记录单元使存储单元存储包括至少一个选择标准和由选择单元使用的至少一个参数的简要记录信息项。每当产生输入内容的摘要时，存储单元存储简要记录信息项。选择单元从存储单元获取过去的简要记录信息项，并且使用至少一个选择标准和至少一个参数来生成摘要，该参数不包括在过去的简要记录信息项中。

2. 发明申请

US20130033591A1 IMAGE PROCESSING DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：图像处理设备，方法和计算机程序产品
公开(公告)号：US20130033591A1
公开(公告)日：2013-02-07
申请号：US13535952
申请日：2012-06-28
申请人： Shihomi TAKAHASHI , Masashi NISHIYAMA , Tomoyuki SHIBATA , Makoto HIROHATA , Masahiro SEKINE , Kaoru SUGITA
发明人： Shihomi TAKAHASHI , Masashi NISHIYAMA , Tomoyuki SHIBATA , Makoto HIROHATA , Masahiro SEKINE , Kaoru SUGITA
IPC分类号： G06K9/46 , H04N7/18
CPC分类号： G06T11/00 , G06K9/48 , G06K9/50
摘要： In an embodiment, an image processing device includes: a first calculating unit; a selecting unit; an extracting unit; a second calculating unit; a determining unit; and a generating unit. The first calculating unit calculates posture information of a subject from a first image including the subject. The selecting unit selects a second image associated with the posture information from a plurality of second images including clothing. The extracting unit extracts a first feature of the subject from a first contour in the first image and extracts a second feature from a second contour in the second image. The second calculating unit calculates a first difference between the first feature and the second feature. The determining unit determines a transparency that is higher as the first difference is larger. The generating unit generates a composite image combining the first image and the second image with the determined transparency.
摘要翻译：在一个实施例中，图像处理装置包括：第一计算单元; 选择单元; 提取单元; 第二计算单元; 决定单位和发电机组。第一计算单元从包括对象的第一图像计算被摄体的姿势信息。选择单元从包括衣服的多个第二图像中选择与姿势信息相关联的第二图像。提取单元从第一图像中的第一轮廓提取对象的第一特征并从第二图像中的第二轮廓提取第二特征。第二计算单元计算第一特征和第二特征之间的第一差值。确定单元确定随着第一差异较大而更高的透明度。生成单元生成以确定的透明度组合第一图像和第二图像的合成图像。

3. 发明授权

US08201700B2 Container for inspection 有权
标题翻译：集装箱检查
公开(公告)号：US08201700B2
公开(公告)日：2012-06-19
申请号：US12448850
申请日：2008-01-18
申请人： Tomoyuki Shibata , Manabu Hosokawa , Hiroaki Hayashi , Natsuki Masuya , Yoshiaki Seto , Shingo Saito , Hidetoshi Kanda
发明人： Tomoyuki Shibata , Manabu Hosokawa , Hiroaki Hayashi , Natsuki Masuya , Yoshiaki Seto , Shingo Saito , Hidetoshi Kanda
IPC分类号： B65D51/20 , B65D51/18 , B65D39/00 , B65D41/00 , B65D41/04 , B65D41/34
CPC分类号： B65D47/36 , B01L3/50825 , B01L2200/026 , B01L2200/141 , B01L2300/044 , B01L2300/0672 , B01L2300/0832 , B65D51/222 , B65D2251/0025 , B65D2251/0087
摘要： Provided is a container 1 for inspection which stores and pours out contents therein, and the container is provided with a container main body 2 having a mouth portion 22 formed thereon, a cover portion 3 attached to the mouth portion 22 to seal the container main body 2, and an opening cap 4 attached to the cover portion 3. The cover portion 3 has a closing wall 34 for closing the mouth portion 22, and the opening cap 4 is provided with an pouring outlet 421, and a cutting portion 431 for cutting the closing wall 34. When the opening cap 4 is attached to the cover portion 3, the cutting section 431 cuts the closing wall 34 to enable pouring out the contents.Thus, in the provided container 1 for inspection, sealing properties of the container main body 2 are ensured by the cover portion 3, and the closing wall 34 of the cover portion 3 is cut by the opening cap 4 attached to the cover portion 3 without removing the cover portion 3, whereby the contents can be poured out.
摘要翻译：本发明提供一种用于检查的容器1，其中存储和倾倒内容物，并且容器设置有容纳在其上的口部22的容器主体2，盖部分3，安装在口部22上以密封容器主体盖部3具有用于封闭口部22的封闭壁34，开口帽4设置有倾倒出口421，切割部431用于切断封闭壁34.当打开盖4附接到盖部分3时，切割部分431切割封闭壁34以便能够倾倒内容物。因此，在所提供的用于检查的容器1中，通过盖部分3确保容器主体2的密封性能，并且盖部分3的封闭壁34被附接到盖部分3的开口盖4切割而没有移除盖部分3，从而可以倒出内容物。

4. 发明授权

US07941573B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07941573B2
公开(公告)日：2011-05-10
申请号：US12146121
申请日：2008-06-25
申请人： Tomoyuki Shibata
发明人： Tomoyuki Shibata
IPC分类号： G06F13/28 , G06F13/38
CPC分类号： G06F13/4243 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C11/4096 , G11C2207/107 , Y02D10/14 , Y02D10/151
摘要： Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.
摘要翻译：数据传输总线充电/放电电流在半导体存储器件中减少。在通过多个总线从发送单元10顺序地将比特序列传送到接收单元20的数据传送装置中，发送电路10包括标志生成电路11和编码电路12.标志生成电路11生成指示是否在通过总线传送的每个比特序列中的连续比特中发生比特反转，并将生成的标志发送到接收单元20.编码电路12基于该标志对比特序列进行编码，以传输到接收单元20.接收单元包括解码电路21，其基于比特序列和标志对比特序列进行解码。

5. 发明授权

US07808848B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07808848B2
公开(公告)日：2010-10-05
申请号：US12394550
申请日：2009-02-27
申请人： Tomoyuki Shibata , Kanji Oishi
发明人： Tomoyuki Shibata , Kanji Oishi
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C17/165 , G11C29/808 , G11C29/846
摘要： In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is arranged.
摘要翻译：在具有可以被独立访问的多个存储体的半导体存储器中，分别以一对一的关系为存储体提供用于代替缺陷存储单元的补偿位寄存器。此外，布置了用于共享每个存储体中的多个补救位寄存器的装置。

6. 发明申请

US20100044337A1 CONTAINER FOR INSPECTION 有权
标题翻译：集装箱检查
公开(公告)号：US20100044337A1
公开(公告)日：2010-02-25
申请号：US12448850
申请日：2008-01-18
申请人： Tomoyuki Shibata , Manabu Hosokawa , Hiroaki Hayashi , Natsuki Masuya , Yoshiaki Seto , Shingo Saito , Hidetoshi Kanda
发明人： Tomoyuki Shibata , Manabu Hosokawa , Hiroaki Hayashi , Natsuki Masuya , Yoshiaki Seto , Shingo Saito , Hidetoshi Kanda
IPC分类号： B65D51/00 , B65D41/34 , B65D51/22
CPC分类号： B65D47/36 , B01L3/50825 , B01L2200/026 , B01L2200/141 , B01L2300/044 , B01L2300/0672 , B01L2300/0832 , B65D51/222 , B65D2251/0025 , B65D2251/0087
摘要： Provided is a container 1 for inspection which stores and pours out contents therein, and the container is provided with a container main body 2 having a mouth portion 22 formed thereon, a cover portion 3 attached to the mouth portion 22 to seal the container main body 2, and an opening cap 4 attached to the cover portion 3. The cover portion 3 has a closing wall 34 for closing the mouth portion 22, and the opening cap 4 is provided with an pouring outlet 421, and a cutting portion 431 for cutting the closing wall 34. When the opening cap 4 is attached to the cover portion 3, the cutting section 431 cuts the closing wall 34 to enable pouring out the contents.Thus, in the provided container 1 for inspection, sealing properties of the container main body 2 are ensured by the cover portion 3, and the closing wall 34 of the cover portion 3 is cut by the opening cap 4 attached to the cover portion 3 without removing the cover portion 3, whereby the contents can be poured out.
摘要翻译：本发明提供一种用于检查的容器1，其中存储和倾倒内容物，并且容器设置有容纳在其上的口部22的容器主体2，盖部分3，安装在口部22上以密封容器主体盖部3具有用于封闭口部22的封闭壁34，开口盖4设置有倾倒出口421，切割部431用于切断封闭壁34.当打开盖4附接到盖部分3时，切割部分431切割封闭壁34以便能够倾倒内容物。因此，在所提供的用于检查的容器1中，通过盖部分3确保容器主体2的密封性能，并且盖部分3的封闭壁34被附接到盖部分3的开口盖4切割而没有移除盖部分3，从而可以倒出内容物。

7. 发明申请

US20090019044A1 PATTERN SEARCH APPARATUS AND METHOD THEREOF 有权
标题翻译：图案搜索装置及其方法
公开(公告)号：US20090019044A1
公开(公告)日：2009-01-15
申请号：US12170597
申请日：2008-07-10
申请人： Tomoyuki Shibata , Osamu Yamaguchi , Toshikazu Wada
发明人： Tomoyuki Shibata , Osamu Yamaguchi , Toshikazu Wada
IPC分类号： G06F7/20 , G06F17/30
CPC分类号： G06F17/30539 , G06K9/00288 , G06K9/6276
摘要： A pattern search apparatus includes a storage unit, a distribution acquisition unit, a hash function unit, a training unit, and a search unit. A cumulative probability distribution of the training pattern on an arbitrary axis is obtained, and hash function each of which divides a probability value are defined based on the cumulative probability distribution.
摘要翻译：图案搜索装置包括存储单元，分发获取单元，散列函数单元，训练单元和搜索单元。获得训练样本在任意轴上的累积概率分布，并且基于累积概率分布来定义每一个划分概率值的散列函数。

8. 发明申请

US20090006687A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090006687A1
公开(公告)日：2009-01-01
申请号：US12146121
申请日：2008-06-25
申请人： Tomoyuki Shibata
发明人： Tomoyuki Shibata
IPC分类号： G06F13/42 , G06F7/38
CPC分类号： G06F13/4243 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C11/4096 , G11C2207/107 , Y02D10/14 , Y02D10/151
摘要： Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.
摘要翻译：数据传输总线充电/放电电流在半导体存储器件中减少。在通过多个总线从发送单元10顺序地将比特序列传送到接收单元20的数据传送装置中，发送电路10包括标志生成电路11和编码电路12.标志生成电路11生成指示是否在通过总线传送的每个比特序列中的连续比特中发生比特反转，并将生成的标志发送到接收单元20.编码电路12基于该标志对比特序列进行编码，以传输到接收单元20.接收单元包括解码电路21，其基于比特序列和标志对比特序列进行解码。

9. 发明申请

US20080062784A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20080062784A1
公开(公告)日：2008-03-13
申请号：US11875390
申请日：2007-10-19
申请人： Tomoyuki Shibata , Kanji Oishi
发明人： Tomoyuki Shibata , Kanji Oishi
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C17/165 , G11C29/808 , G11C29/846
摘要： In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is arranged.
摘要翻译：在具有可以被独立访问的多个存储体的半导体存储器中，分别以一对一的关系为存储体提供用于代替缺陷存储单元的补偿位寄存器。此外，布置了用于共享每个存储体中的多个补救位寄存器的装置。

10. 发明授权

US06958638B2 Slew rate controlling method and system for output data 失效
标题翻译：输出数据的压摆率控制方法和系统
公开(公告)号：US06958638B2
公开(公告)日：2005-10-25
申请号：US10681836
申请日：2003-10-09
申请人： Tomoyuki Shibata , Kanji Oishi
发明人： Tomoyuki Shibata , Kanji Oishi
IPC分类号： H03K5/12 , G11C11/409 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K3/017
CPC分类号： H03K19/00384
摘要： A slew rate controlling system for output data is provided which is capable of improving an output data window even when change in a potential difference between a first power supply (VDD) to be used for outputting and a second power supply (VDDQ) to be used internally occurs. The slew rate controlling system is achieved by using a VDD-VDDQ potential difference detecting circuit to detect a decrease in a potential difference between the first power supply (VDD) and the second power supply (VDDQ) and to produce a first signal with specified timing and to detect an increase in a potential difference between the first power supply (VDD) and the second power supply (VDDQ) and to produce a second signal and by using a slew rate controlling circuit to exert control, when the first signal is significant, to enlarge a transition speed in a fall of output data and to exert control, when the second signal is significant, to enlarge the transition speed in a rise of output data and to produce output data.
摘要翻译：提供一种用于输出数据的转换速率控制系统，其即使在要用于输出的第一电源（VDD）和要使用的第二电源（VDDQ）之间的电位差的变化时也能够改善输出数据窗口内部发生。通过使用VDD-VDDQ电位差检测电路来检测第一电源（VDD）和第二电源（VDDQ）之间的电位差的降低，并且产生具有指定定时的第一信号来实现转换速率控制系统并且检测第一电源（VDD）和第二电源（VDDQ）之间的电位差的增加并产生第二信号，并且通过使用转换速率控制电路进行控制，当第一信号有效时，为了在输出数据的下降中放大转换速度并且在第二信号有效时施加控制，以增大输出数据的上升中的转换速度并产生输出数据。

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