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    • 4. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT AND TRANSMITTER APPARATUS HAVING THE SAME
    • 半导体集成电路及其发送装置
    • US20100245663A1
    • 2010-09-30
    • US12376405
    • 2007-07-31
    • Manabu KawabataRyogo YanagisawaToru IwataHirokazu Sugimoto
    • Manabu KawabataRyogo YanagisawaToru IwataHirokazu Sugimoto
    • H04N7/01G06F1/04H04N5/05
    • H03K5/135H03L7/18H03M9/00H04L7/0008
    • A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
    • 一种用于接收并行数据信号和第一时钟信号并输出​​串行数据信号和第二时钟信号的半导体集成电路(10D),其中第一时钟产生电路(15)产生通过将第一时钟 信号X / Y。 第二时钟发生电路(11)具有可变的传输特性,并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分(12)将已被转换的并行数据信号 缩放器(16),与第四时钟信号同步地连接到串行数据信号。 分频器(13)产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器(14)有选择地输出第三和第五时钟​​信号之一作为第二时钟信号。
    • 5. 发明授权
    • Phase adjustment circuit
    • 相位调整电路
    • US07782103B2
    • 2010-08-24
    • US11513023
    • 2006-08-31
    • Toru Iwata
    • Toru Iwata
    • H03L7/06
    • H03L7/0814H03L7/07H03L7/0805H03L7/0812H04L7/0037H04L7/0337
    • A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
    • 一种相位调整电路,用于离散地调整数据信号的相位和时钟信号的相位,所述相位调整电路包括:延迟线,用于延迟所述时钟信号以产生延迟的时钟信号; 相位比较器,用于比较数据信号的相位与延迟的时钟信号的相位; 延迟控制部分,用于基于来自相位比较器的比较结果输出延迟控制信号; 以及延迟控制部分,用于基于时钟信号的频率输出延迟控制信号。 延迟线基于控制信号确定相对于时钟信号的延迟时钟信号的延迟量。
    • 6. 发明授权
    • High-altitude capable wide velocity range flight velocity vector measurement probe and measurement system
    • 高空能力宽速度范围飞行速度矢量测量探头和测量系统
    • US07480548B2
    • 2009-01-20
    • US11224030
    • 2005-09-13
    • Masashi ShigemiAkira KoikeMakoto UenoTomonari HirotaniTeruomi NakayaHiroshi WakaiToru Iwata
    • Masashi ShigemiAkira KoikeMakoto UenoTomonari HirotaniTeruomi NakayaHiroshi WakaiToru Iwata
    • G01P5/165G01P5/175
    • G01P5/175G01C5/005G01P5/16G01P13/025
    • It is an object of the present invention to solve the problem of a drop in precision in conventional systems using a square pyramid type five-hole probe due to the drop in atmospheric pressure in high altitude ranges, and to provide a wide velocity range flight velocity vector measurement system that can prevent a drop in measurement precision. Furthermore, it is also an object of the present invention to provide a method for eliminating the effects of detection fluctuations caused by adhering water droplets, ice particles or dust in a wide velocity range flight velocity vector measurement system. The flight velocity vector measurement probe of the present invention comprises means in which a static pressure hole is formed in the tube wall surface of the probe, so that a static pressure value is obtained from the pressure detected by this static pressure hole, the Mach number M is calculated on the basis of an equation approximated by a fourth-order polynomial of the static pressure/total pressure signal and the angle of attack, and in cases where an abnormal detection value is detected, this is replaced by the preceding detection value.
    • 本发明的一个目的是解决由于在高海拔范围内的大气压力下降而使用方形棱锥型五孔探针的常规系统的精度下降的问题,并且提供宽的速度范围飞行速度 矢量测量系统,可以防止测量精度下降。 此外,本发明的另一个目的是提供一种消除在宽速度范围飞行速度矢量测量系统中粘附水滴,冰粒或灰尘引起的检测波动的影响的方法。 本发明的飞行速度矢量测量探头包括在探针的管壁表面中形成静压孔的装置,从而由​​该静压孔检测到的压力获得静压值,马赫数 基于由静压/总压力信号的四次多项式近似的方程式计算出M,并且在检测到异常检测值的情况下,将其替换为前一检测值。
    • 7. 发明授权
    • Indoor apparatus for air conditioner
    • 空调室内机
    • US07204096B2
    • 2007-04-17
    • US10533200
    • 2003-10-30
    • Toru IwataMasakazu Hirai
    • Toru IwataMasakazu Hirai
    • F25D17/06
    • F24F1/0007F24F1/0011F24F1/0022F24F2001/0037
    • An air discharge outlet comprises line air discharge outlets (35) and corner air discharge outlets (36). The line air discharge outlets (35) are so formed as to extend, respectively, along four sides of a casing bottom part having four side parts and four corner parts wherein the side and corner parts are formed in contiguous relationship to one another. The corner air discharge outlets (36) are formed, respectively, in the four casing corner parts so that each corner air discharge outlet (36) establishes connection between adjacent ones of the line air discharge outlets (35). And, each line air discharge outlet (35) is provided with a swing vane (38) swingable about a longitudinal shaft (41) of each line air discharge outlet (35). Each corner air discharge outlet (36) is provided with a fixed stationary vane (39).
    • 空气排出口包括排气出口(35)和角空气排出口(36)。 线排出口35形成为分别沿着具有四个侧面部分和四个拐角部分的壳体底部的四个侧面延伸,其中侧部和拐角部分彼此连续地形成。 角空气排出口36分别形成在四个壳体角部,使得每个角空气排出口36建立相邻的排气出口35之间的连接。 并且,每排排气口(35)设置有可围绕每排排气口(35)的纵轴(41)摆动的摆动叶片(38)。 每个角空气排出口(36)设置有固定静止叶片(39)。
    • 8. 发明申请
    • Phase adjustment circuit
    • 相位调整电路
    • US20070080728A1
    • 2007-04-12
    • US11513023
    • 2006-08-31
    • Toru Iwata
    • Toru Iwata
    • H03L7/06
    • H03L7/0814H03L7/07H03L7/0805H03L7/0812H04L7/0037H04L7/0337
    • A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
    • 一种相位调整电路,用于离散地调整数据信号的相位和时钟信号的相位,所述相位调整电路包括:延迟线,用于延迟所述时钟信号以产生延迟的时钟信号; 相位比较器,用于比较数据信号的相位与延迟的时钟信号的相位; 延迟控制部分,用于基于来自相位比较器的比较结果输出延迟控制信号; 以及延迟控制部分,用于基于时钟信号的频率输出延迟控制信号。 延迟线基于控制信号确定相对于时钟信号的延迟时钟信号的延迟量。