专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08891305B2 Apparatuses and methods involving accessing distributed sub-blocks of memory cells 有权
标题翻译：涉及访问存储器单元的分布式子块的装置和方法
公开(公告)号：US08891305B2
公开(公告)日：2014-11-18
申请号：US13590926
申请日：2012-08-21
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C7/00 , G11C7/02 , G11C8/12 , G11C8/16 , G11C8/18 , G11C11/4087 , G11C13/0004 , G11C13/003
摘要： Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.
摘要翻译：描述了访问存储器单元的分布式子块的装置和方法。在一种这样的方法中，存储器阵列中的存储器单元的分布式子块能够被同时访问。描述其他实施例。

2. 发明授权

US08837222B2 Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate 有权
标题翻译：包括具有包括单晶半导体材料的主体区域和/或其位于衬底中的栅极的至少一部分的选择晶体管的方法和装置
公开(公告)号：US08837222B2
公开(公告)日：2014-09-16
申请号：US13282237
申请日：2011-10-26
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , H01L21/04 , H01L27/115
CPC分类号： H01L27/11556 , G11C16/04 , G11C16/0408 , H01L21/04 , H01L27/11524 , H01L27/11551 , H01L29/04 , H01L29/16
摘要： Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.
摘要翻译：一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于所述装置的不同级别的存储单元和耦合到所述存储单元串的选择晶体管。在这些装置中的至少一个中，选择晶体管可以包括包括单晶半导体材料的主体区域。描述包括附加装置和方法的其他实施例。

3. 发明授权

US08797804B2 Vertical memory with body connection 有权
标题翻译：垂直记忆与身体连接
公开(公告)号：US08797804B2
公开(公告)日：2014-08-05
申请号：US13561946
申请日：2012-07-30
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/06 , G11C16/08
CPC分类号： G11C5/06 , G11C16/04 , G11C16/06 , G11C16/08 , H01L27/11529 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.
摘要翻译：装置的实施例包括基板，主体半导体，主体半导体上的垂直存储器存取线堆叠以及与主体半导体的主体连接。

4. 发明授权

US08681561B2 Apparatuses and methods including memory write operation 有权
标题翻译：包括存储器写入操作的设备和方法
公开(公告)号：US08681561B2
公开(公告)日：2014-03-25
申请号：US13214841
申请日：2011-08-22
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418
摘要： Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括具有耦合到存储器单元的存储器单元和存取线的装置和方法。在一种这样的装置中，接入线路包括第一接入线路和第二接入线路。第一条接入线可以与第二条接入线相邻。存储器单元包括与第二访问线相关联的存储单元。模块可以被配置为在访问与第二接入线路相关联的存储器单元的操作期间将电压施加到第一接入线路，并且在第二接入线路的时间间隔的至少一部分期间将第二接入线路置于浮置状态的操作。描述包括附加装置和方法的其它实施例。

5. 发明授权

US08675420B2 Devices and systems including enabling circuits 有权
标题翻译：设备和系统包括启用电路
公开(公告)号：US08675420B2
公开(公告)日：2014-03-18
申请号：US13116914
申请日：2011-05-26
申请人： Toru Tanzawa , Ali Feiz Zarrin Ghalam
发明人： Toru Tanzawa , Ali Feiz Zarrin Ghalam
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C5/143 , G11C7/1066 , G11C7/1087 , G11C7/1093
摘要： Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.
摘要翻译：描述包括使能电路的设备和系统的示例。可以使用两个电压源来操作设备的不同部分，包括外围电路和I / O电路。当一个或多个器件的外围电路的电源被禁止时，该器件的I / O电路可能被禁止。在一些示例中，可以通过消除或减少通过I / O电路的DC电流路径来部分地节省功率。

6. 发明申请

US20140063959A1 MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE 有权
公开(公告)号：US20140063959A1
公开(公告)日：2014-03-06
申请号：US13599962
申请日：2012-08-30
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/24 , G11C16/26
摘要： Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

7. 发明申请

US20140061849A1 THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH 有权
标题翻译：具有减少接触长度的三维装置
公开(公告)号：US20140061849A1
公开(公告)日：2014-03-06
申请号：US13599900
申请日：2012-08-30
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： H01L27/10 , H01L21/768 , H01L21/82
CPC分类号： H01L27/108 , H01L21/74 , H01L27/0207 , H01L27/11 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括装置和方法，包括具有交替电平的半导体材料和电介质材料的存储器阵列，其具有在交替电平上形成的存储器单元串。一种这样的设备包括基本上形成在衬底的空腔内的存储器阵列。外围电路可以与衬底的表面相邻并且与存储器阵列相邻地形成。描述附加的装置和方法。

8. 发明授权

US08537620B2 Random telegraph signal noise reduction scheme for semiconductor memories 有权
标题翻译：用于半导体存储器的随机电报信号降噪方案
公开(公告)号：US08537620B2
公开(公告)日：2013-09-17
申请号：US13480378
申请日：2012-05-24
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C7/00 , G11C16/0408 , G11C16/10 , G11C16/12 , G11C16/3459
摘要： Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.
摘要翻译：提供的实施例包括一种方法，包括向所选择的存储单元提供第一脉冲栅极信号，其中脉冲栅极信号在一段时间段内在第一电压电平和第二电压电平之间交替并感测数据线响应以确定存储的数据在选定的单元格内存上。另外的实施例提供一种包括存储器件的系统，该存储器件具有耦合到NAND存储器单元的多个访问线路的调节器电路，以及切换电路，被配置为顺序地将多个接入线路中的至少一个在第一电压电平以及基于输入信号的第二电压电平。

9. 发明授权

US08466664B2 Voltage trimming 有权
公开(公告)号：US08466664B2
公开(公告)日：2013-06-18
申请号：US13225365
申请日：2011-09-02
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/04 , G11C16/0483 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028 , H02M2001/0025
摘要： Embodiments are provided that include a memory die, memory devices, and methods, such as those comprising a voltage generator, including an output voltage and an adjustment circuit configured to cause adjustment of the output voltage based on a latch signal. Further one such method includes applying an input voltage to an input of a voltage generator, adjusting the input voltage to an adjusted voltage, comparing the adjusted voltage to a reference voltage, generating trim data based on the comparison and storing the trim data.

10. 发明申请

US20130028023A1 APPARATUSES AND METHODS INCLUDING MEMORY ARRAY AND DATA LINE ARCHITECTURE 有权
标题翻译：包括内存阵列和数据线架构的设备和方法
公开(公告)号：US20130028023A1
公开(公告)日：2013-01-31
申请号：US13192248
申请日：2011-07-27
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , H01L21/8239
CPC分类号： G11C16/0483 , G11C5/025 , G11C5/06 , G11C16/107 , G11C2213/71 , H01L27/1052 , H01L27/11529 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括具有位于器件的不同器件级别中的存储器单元，位于器件的衬底中的晶体管的至少一部分以及耦合到晶体管和存储器单元的数据线的器件和方法。数据线可以位于晶体管和存储单元之间。描述包括附加装置和方法的其它实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式