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1. 发明申请

US20090122188A1 IMAGE DISPLAY DEVICE AND METHOD 审中-公开
标题翻译：图像显示装置和方法
公开(公告)号：US20090122188A1
公开(公告)日：2009-05-14
申请号：US12091166
申请日：2006-10-11
申请人： Toshiharu Hanaoka , Kenichiroh Yamamoto , Hiroyuki Furukawa , Masafumi Ueno , Takashi Yoshii
发明人： Toshiharu Hanaoka , Kenichiroh Yamamoto , Hiroyuki Furukawa , Masafumi Ueno , Takashi Yoshii
IPC分类号： H04N7/01
CPC分类号： H04N5/145 , G09G3/3648 , G09G2320/0261 , G09G2320/106 , G09G2340/0435 , G09G2340/16 , H04N7/0127 , H04N7/014
摘要： An image display device comprising a frame rate converting (FRC) portion can prevent image degradation at a screen boundary part attributed to the FRC processing when displaying an image obtained by combining a plurality of screens. The image display device comprises an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between frames of the input image signal and a screen combining portion 13 for combining a plurality of screens. When displaying an image obtained by combining a plurality of screens, the screen combining portion 13 combines a plurality of screens by matching a motion detection block boundary when performing the motion compensation process by the FRC portion 10 with the respective screen boundaries of the plurality of screens.
摘要翻译：包括帧速率转换（FRC）部分的图像显示装置可以防止当显示通过组合多个画面而获得的图像时归因于FRC处理的画面边界部分处的图像劣化。图像显示装置包括：FRC部分10，用于通过内插输入图像信号的帧之间的运动补偿处理的图像信号和用于组合多个屏幕的屏幕组合部分13来转换输入图像信号的帧数; 。当显示通过组合多个屏幕而获得的图像时，屏幕组合部分13通过使用FRC部分10执行运动补偿处理时的运动检测块边界与多个屏幕的各个屏幕边界匹配来组合多个屏幕。

2. 发明授权

US5877770A Texture pattern memory circuit for providing plural texel data in response to a single access operation 失效
标题翻译：纹理图案存储电路，用于响应于单次访问操作提供多个纹理数据
公开(公告)号：US5877770A
公开(公告)日：1999-03-02
申请号：US634806
申请日：1996-04-19
申请人： Toshiharu Hanaoka
发明人： Toshiharu Hanaoka
IPC分类号： G09G5/39 , G06F12/00 , G06F12/06 , G06T1/60 , G06T11/20 , G06T15/00 , G06T11/40
CPC分类号： G06T15/04
摘要： This texture pattern memory circuit is composed of a multi-texture pattern memory, a writing device and a texel selector. The multi-texture pattern memory includes an adder, a subtracter, selectors, 1st to 4th address converting devices, and 1st to 4th memory modules. The texel selector selects only the necessary data from the texel data outputted from the multi-texture pattern memory.
摘要翻译：该纹理图案存储电路由多纹理图形存储器，写入装置和纹素选择器构成。多纹理图案存储器包括加法器，减法器，选择器，第1至第4地址转换器件以及第1至第4存储器模块。纹理选择器仅从多纹理图案存储器输出的纹理数据中仅选择必要的数据。

3. 发明申请

US20090059068A1 IMAGE DISPLAY DEVICE AND METHOD 有权
标题翻译：图像显示装置和方法
公开(公告)号：US20090059068A1
公开(公告)日：2009-03-05
申请号：US12066218
申请日：2006-09-20
申请人： Toshiharu Hanaoka , Kenichiroh Yamamoto , Hiroyuki Furukawa , Masafumi Ueno , Yasuhiro Yoshida
发明人： Toshiharu Hanaoka , Kenichiroh Yamamoto , Hiroyuki Furukawa , Masafumi Ueno , Yasuhiro Yoshida
IPC分类号： H04N7/01
CPC分类号： G09G3/20 , G09G2320/106 , G09G2340/0435 , G09G2340/125 , H04N5/145 , H04N5/44504 , H04N5/45 , H04N7/013 , H04N7/014 , H04N21/4316 , H04N21/44008 , H04N21/440281 , H04N21/4435
摘要： In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portion 14 for superposing an OSD signal on the input image signal, and a controlling portion 15. The FRC portion 10 has a motion vector detecting portion 11e for detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portion 11f for allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portion 12d for generating an interpolation frame from the interpolation vector. When the OSD signal is superposed on the input image signal, the controlling portion 15 disables the motion compensation process of the FRC portion 10 by making the motion vector detected by the motion vector detecting portion 11e 0 vector.
摘要翻译：在具有帧速率转换（FRC）部分的图像显示装置中，可以防止归因于FRC处理的诸如OSD和PinP的组合图像显示部分的图像劣化。图像显示装置包括：FRC部分10，用于通过内插在输入图像信号的帧之间进行运动补偿处理的图像信号来转换输入图像信号的帧数; 用于将OSD信号叠加在输入图像信号上的OSD处理部分14以及控制部分15.FRC部分10具有运动矢量检测部分11e，用于检测输入图像信号的帧之间的运动矢量，插值矢量用于基于运动矢量信息在帧之间分配插值矢量的评估部分11f和用于从插值向量生成内插帧的内插帧产生部分12d。当OSD信号叠加在输入图像信号上时，控制部分15通过使运动矢量检测部分11e 0矢量检测到的运动矢量来禁止FRC部分10的运动补偿处理。

4. 发明授权

US5590249A Three dimensional sprite rendering apparatus and method 失效
标题翻译：三维精灵渲染设备和方法
公开(公告)号：US5590249A
公开(公告)日：1996-12-31
申请号：US414234
申请日：1995-03-31
申请人： Toshiharu Hanaoka
发明人： Toshiharu Hanaoka
IPC分类号： G09G5/36 , G06T13/20 , G09G5/377 , G09G5/38 , G06T15/40
CPC分类号： G06T15/405
摘要： A three dimensional sprite rendering apparatus for producing three dimensional graphic images includes a three dimensional graphic circuit for producing backgrounds of three dimensional graphics and outputting pixel data for each pixel of the backgrounds, and a first buffer storing depth data for each pixel of the backgrounds. The apparatus further includes a voxel character control register for storing control data for voxel characters, a voxel character memory storing geometric data for voxel characters, a volume rendering circuit connected to the voxel character control register and the voxel character memory for producing graphics of voxel characters and outputting pixel data for each pixel of the voxel characters, and a second buffer storing depth data for each pixel of the voxel characters. A depth comparator is connected to the first and second buffers for comparing the depth of a three dimensional background graphic with the depth of a voxel character graphic and generating a control signal according to a result of comparison. An image generation circuit receives the pixel data of backgrounds and the pixel data of voxel characters as well as the control signal, and synthesizes two pixel data inputs according to the control signal.
摘要翻译：用于产生三维图形图像的三维精灵渲染装置包括用于产生三维图形背景并输出每个背景像素的像素数据的三维图形电路，以及存储每个背景像素的深度数据的第一缓冲器。该装置还包括用于存储体素字符的控制数据的体元字符控制寄存器，存储用于体元字符的几何数据的体元字符存储器，连接到体素字符控制寄存器的体绘制电路和用于产生体元字符图形的体元字符存储器并且输出所述体元字符的每个像素的像素数据，以及存储所述体元字符的每个像素的深度数据的第二缓冲器。深度比较器连接到第一和第二缓冲器，用于将三维背景图形的深度与体素字符图形的深度进行比较，并根据比较结果生成控制信号。图像生成电路接收背景的像素数据和体元字符的像素数据以及控制信号，并且根据控制信号合成两个像素数据输入。

5. 发明授权

US07965303B2 Image displaying apparatus and method, and image processing apparatus and method 有权
标题翻译：图像显示装置和方法，以及图像处理装置和方法
公开(公告)号：US07965303B2
公开(公告)日：2011-06-21
申请号：US11817141
申请日：2007-02-21
申请人： Toshiharu Hanaoka , Yasuhiro Yoshida , Masafumi Ueno , Hiroyuki Furukawa , Kenichiroh Yamamoto , Takashi Yoshii
发明人： Toshiharu Hanaoka , Yasuhiro Yoshida , Masafumi Ueno , Hiroyuki Furukawa , Kenichiroh Yamamoto , Takashi Yoshii
IPC分类号： G09G5/00 , G09G5/02 , H04N7/14 , H04N11/04 , G06K9/40 , G06K9/32
CPC分类号： H04N5/144 , G09G3/2096 , G09G3/3648 , G09G2320/0261 , G09G2320/106 , G09G2340/14 , G09G2340/16 , H04N7/013 , H04N7/014
摘要： In an image displaying apparatus including a motion compensated rate converting (FRC) portion, deterioration of image quality is prevented in an image having a high-speed region and a low-speed region mixed. The FRC portion includes a motion vector detecting portion 11e and an interpolation frame generating portion 12b. The motion vector detecting portion 11e includes a first region detecting means 112e1 that detects a first region (high-speed region) including a motion amount equal to or greater than a first predetermined amount from an input image signal, a second region detecting means 112e2 that detects a second region (low-speed region) including a motion amount equal to or less than a second predetermined amount from the input image signal, and a third region detecting means 113e that detects a still region from an inter-frame difference of the input image signal. The interpolation frame generating portion 12b executes a motion compensated interpolation process using motion vectors for the still region in the first region (background) and executes a zero-vector interpolation process for the still region in the second region (foreground).
摘要翻译：在包括运动补偿速率转换（FRC）部分的图像显示装置中，在具有高速区域和低速区域的图像混合的情况下，防止了图像质量的劣化。 FRC部分包括运动矢量检测部分11e和内插帧产生部分12b。运动矢量检测部分11e包括：第一区域检测装置112e1，其从输入图像信号检测包括等于或大于第一预定量的运动量的第一区域（高速区域）;第二区域检测装置112e2，从输入图像信号检测包括等于或小于第二预定量的运动量的第二区域（低速区域）以及从输入的帧间差异检测静止区域的第三区域检测装置113e 图像信号。内插帧生成部分12b使用第一区域（背景）中的静止区域的运动矢量来执行运动补偿插值处理，并对第二区域（前景）中的静止区域执行零矢量插值处理。

6. 发明授权

US6078334A 3-D texture mapping processor and 3-D image rendering system using the same 失效
标题翻译： 3-D纹理映射处理器和3-D图像渲染系统使用相同
公开(公告)号：US6078334A
公开(公告)日：2000-06-20
申请号：US64036
申请日：1998-04-22
申请人： Toshiharu Hanaoka , Hiroaki Yabe , Takeshi Hashimoto
发明人： Toshiharu Hanaoka , Hiroaki Yabe , Takeshi Hashimoto
IPC分类号： G06T15/00 , G06T15/02 , G06T15/04 , G06F15/00
CPC分类号： G06T15/04
摘要： A three-dimensional image rendering portion, based on image data, performs geometric transformation, projection transformation, etc. and further applies texture data from the texture memory onto polygons, to thereby generate graphic data of a 3-D image. This graphic data is used as pixel data for a frame of image and written into the frame memory. A 3-D texture modeling value generating circuit performs arithmetic operations on 3-D texture modeling values of asperities of the textures, using coordinate data given from the 3-D image rendering portion, bump data stored in the texture memory and parameters stored in the register. These 3-D texture modeling values are provided to 3-D texture modeling circuit where, based on these values, the data from the frame memory is formed into a 3-dimensional form, which in turn is displayed on the display unit.
摘要翻译：基于图像数据的三维图像渲染部分执行几何变换，投影变换等，并且进一步将纹理数据从纹理存储器应用于多边形，从而生成3-D图像的图形数据。该图形数据用作图像帧的像素数据并写入帧存储器。 3-D纹理建模值生成电路使用从3D图像呈现部分给出的坐标数据，存储在纹理存储器中的凹凸数据和存储在纹理存储器中的参数，对纹理粗糙度的3-D纹理建模值执行算术运算寄存器。这些3-D纹理建模值被提供给3-D纹理建模电路，其中基于这些值，来自帧存储器的数据被形成为三维形式，其又显示在显示单元上。

7. 发明授权

US09881535B2 Image display device and method 有权
公开(公告)号：US09881535B2
公开(公告)日：2018-01-30
申请号：US12066218
申请日：2006-09-20
申请人： Toshiharu Hanaoka , Kenichiroh Yamamoto , Hiroyuki Furukawa , Masafumi Ueno , Yasuhiro Yoshida
发明人： Toshiharu Hanaoka , Kenichiroh Yamamoto , Hiroyuki Furukawa , Masafumi Ueno , Yasuhiro Yoshida
IPC分类号： H04N7/01 , G09G3/20 , H04N5/14 , H04N5/445 , H04N5/45 , H04N21/431 , H04N21/44 , H04N21/4402 , H04N21/443
CPC分类号： G09G3/20 , G09G2320/106 , G09G2340/0435 , G09G2340/125 , H04N5/145 , H04N5/44504 , H04N5/45 , H04N7/013 , H04N7/014 , H04N21/4316 , H04N21/44008 , H04N21/440281 , H04N21/4435
摘要： In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portion 14 for superposing an OSD signal on the input image signal, and a controlling portion 15. The FRC portion 10 has a motion vector detecting portion 11e for detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portion 11f for allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portion 12d for generating an interpolation frame from the interpolation vector. When the OSD signal is superposed on the input image signal, the controlling portion 15 disables the motion compensation process of the FRC portion 10 by making the motion vector detected by the motion vector detecting portion 11e 0 vector.

8. 发明申请

US20090231314A1 IMAGE DISPLAYING APPARATUS AND METHOD, AND IMAGE PROCESSING APPARATUS AND METHOD 有权
标题翻译：图像显示装置和方法以及图像处理装置和方法
公开(公告)号：US20090231314A1
公开(公告)日：2009-09-17
申请号：US11817141
申请日：2007-02-21
申请人： Toshiharu Hanaoka , Yasuhiro Yoshida , Masafumi Ueno , Hiroyuki Furukawa , Kenichiroh Yamamoto , Takashi Yoshii
发明人： Toshiharu Hanaoka , Yasuhiro Yoshida , Masafumi Ueno , Hiroyuki Furukawa , Kenichiroh Yamamoto , Takashi Yoshii
IPC分类号： G09G5/00 , G09G3/34
CPC分类号： H04N5/144 , G09G3/2096 , G09G3/3648 , G09G2320/0261 , G09G2320/106 , G09G2340/14 , G09G2340/16 , H04N7/013 , H04N7/014
摘要： In an image displaying apparatus including a motion compensated rate converting (FRC) portion, deterioration of image quality is prevented in an image having a high-speed region and a low-speed region mixed. The FRC portion includes a motion vector detecting portion 11e and an interpolation frame generating portion 12b. The motion vector detecting portion 11e includes a first region detecting means 112e1 that detects a first region (high-speed region) including a motion amount equal to or greater than a first predetermined amount from an input image signal, a second region detecting means 112e2 that detects a second region (low-speed region) including a motion amount equal to or less than a second predetermined amount from the input image signal, and a third region detecting means 113e that detects a still region from an inter-frame difference of the input image signal. The interpolation frame generating portion 12b executes a motion compensated interpolation process using motion vectors for the still region in the first region (background) and executes a zero-vector interpolation process for the still region in the second region (foreground).
摘要翻译：在包括运动补偿速率转换（FRC）部分的图像显示装置中，在具有高速区域和低速区域的图像混合的情况下，防止了图像质量的劣化。 FRC部分包括运动矢量检测部分11e和内插帧产生部分12b。运动矢量检测部分11e包括：第一区域检测装置112e1，其从输入图像信号检测包括等于或大于第一预定量的运动量的第一区域（高速区域）;第二区域检测装置112e2，从输入图像信号检测包括等于或小于第二预定量的运动量的第二区域（低速区域）以及从输入的帧间差异检测静止区域的第三区域检测装置113e 图像信号。内插帧生成部分12b使用第一区域（背景）中的静止区域的运动矢量来执行运动补偿插值处理，并对第二区域（前景）中的静止区域执行零矢量插值处理。

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