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1. 发明授权

US09501668B2 Secure video ouput path 有权
标题翻译：安全视频输出路径
公开(公告)号：US09501668B2
公开(公告)日：2016-11-22
申请号：US14036263
申请日：2013-09-25
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , Prashant Dewan , David M. Durham , Balaji Vembu , Xiaozhu Kang , Scott Janus , Jason Martin , Vincent R. Scarlata
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , Prashant Dewan , David M. Durham , Balaji Vembu , Xiaozhu Kang , Scott Janus , Jason Martin , Vincent R. Scarlata
IPC分类号： H04N7/167 , G06F21/82 , G06F21/84 , G06F21/85 , H04N21/41 , H04N21/4143 , H04N21/4367
CPC分类号： G06F21/82 , G06F21/84 , G06F21/85 , H04N21/4122 , H04N21/4143 , H04N21/4367
摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.
摘要翻译：用于将输出表面位图安全传递到显示引擎的系统和方法。一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述体系结构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在所述体系结构保护的存储器中的指令，建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥具有第二加密密钥的加密密钥。

2. 发明授权

US09092644B2 Method and system for protecting memory information in a platform 有权
标题翻译：保护平台内存信息的方法和系统
公开(公告)号：US09092644B2
公开(公告)日：2015-07-28
申请号：US13976935
申请日：2011-12-28
申请人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
发明人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
IPC分类号： G06F21/64 , H04L9/06 , G06F12/14 , G06F21/78 , G06F21/79
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/78 , G06F21/79 , H04L9/0643 , H04L2209/12
摘要： A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on “Global and Local Counters”. This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the “tweak” used in the XTS encryption without sacrificing cryptographic strength.
摘要翻译：一种方法和系统，为存储在存储器中的敏感信息提供有效，可扩展且低成本的保密性，完整性和重放保护解决方案，并防止攻击者观察和/或修改系统的状态。在本发明的一个实施例中，系统通过经由XTS调整加密模式对其存储器内容具有强大的硬件保护，其中基于“全局和本地计数器”导出调整。该方案提供了通过允许多个计数器级别为任何大小的存储器提供芯片区域高效的重放保护，并有助于使用小型计数器来导出XTS加密中使用的“调整”，而不会牺牲加密强度。

3. 发明授权

US08799673B2 Seamlessly encrypting memory regions to protect against hardware-based attacks 有权
标题翻译：无缝加密内存区域以防止基于硬件的攻击
公开(公告)号：US08799673B2
公开(公告)日：2014-08-05
申请号：US12651432
申请日：2009-12-31
申请人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
发明人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
IPC分类号： H04L29/06
CPC分类号： G06F12/1408 , G06F12/1441 , G06F2212/1052
摘要： Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction.
摘要翻译：公开了系统，装置和方法，并且用于无缝地保护存储器区域以防止基于硬件的攻击。在一个实施例中，一种装置包括解码器，控制逻辑和加密逻辑。解码器是对处理器和存储器映射的输入/输出空间之间的事务进行解码。控制逻辑是将事务从内存映射的输入/输出空间重定向到系统内存。密码逻辑是对数据进行交易操作。

4. 发明申请

US20140196155A1 DIGITAL RIGHTS MANAGEMENT (DRM) LOCKER 审中-公开
标题翻译：数字权限管理（DRM）锁
公开(公告)号：US20140196155A1
公开(公告)日：2014-07-10
申请号：US14204924
申请日：2014-03-11
申请人： Christopher J. McConnell , Uday R. Savagaonkar
发明人： Christopher J. McConnell , Uday R. Savagaonkar
IPC分类号： H04L29/06
CPC分类号： H04L63/10 , G06F21/10 , H04L2463/101
摘要： Methods, apparatuses and storage medium associated digital rights management (DRM) using DRM locker is disclosed herein. In embodiments, a DRM locker is provided to a client device. The DRM locker may be configured to store a number of DRM licenses or keys for a number of DRM protected contents. The DRM locker, on presentation of an associated locker key, may respond to a request for one or more of the stored DRM licenses or keys, to enable consumption of the corresponding DRM protected contents using the client device. Other embodiments may be disclosed or claimed.
摘要翻译：本文公开了使用DRM储物柜的方法，装置和存储介质相关联的数字版权管理（DRM）。在实施例中，DRM存储器被提供给客户端设备。 DRM存储器可以被配置为存储用于多个受DRM保护的内容的许多DRM许可证或密钥。 DRM存储器在呈现相关联的密钥时，可以响应对所存储的DRM许可证或密钥中的一个或多个的请求，以使得能够使用客户端设备消费相应的受DRM保护的内容。可以公开或要求保护其他实施例。

5. 发明申请

US20140123235A1 Allocating Memory Access Control Policies 有权
标题翻译：分配内存访问控制策略
公开(公告)号：US20140123235A1
公开(公告)日：2014-05-01
申请号：US13993421
申请日：2011-12-28
申请人： Prashant Dewan , Jason Martin , Uday R. Savagaonkar , Carlos V. Rozas
发明人： Prashant Dewan , Jason Martin , Uday R. Savagaonkar , Carlos V. Rozas
IPC分类号： G06F21/62
CPC分类号： G06F21/62 , G06F21/53
摘要： Enabling access control caches for co-processors to be charged using a VMX-nonroot instruction. As a result a transition to VMX-root is not needed, saving the cycles involved in such a transition.
摘要翻译：使用VMX-nonroot指令为协处理器启用访问控制高速缓存。因此，不需要转换到VMX-root，从而节省了这种转换所涉及的周期。

6. 发明申请

US20140101461A1 PARALLELIZED COUNTER TREE WALK FOR LOW OVERHEAD MEMORY REPLAY PROTECTION 有权
标题翻译：并行平衡计数器用于低过载存储器重放保护
公开(公告)号：US20140101461A1
公开(公告)日：2014-04-10
申请号：US13646105
申请日：2012-10-05
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/71
摘要： A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.
摘要翻译：处理器包括为存储器区域提供重放和保密性保护的存储器加密引擎。存储器加密引擎沿着计数器树结构执行低架构并行化的树行走。存储器加密引擎在接收到对受保护的存储器区域的传入读取请求时，执行依赖性检查操作以识别传入的读取请求与进程内请求之间的依赖关系，并且当进程内请求是读取请求时，去除依赖关系目前尚未暂停。

7. 发明申请

US20140096068A1 DEVICE AND METHOD FOR SECURE USER INTERFACE GESTURE PROCESSING USING PROCESSOR GRAPHICS 有权
标题翻译：使用处理器图形确保用户界面姿态处理的设备和方法
公开(公告)号：US20140096068A1
公开(公告)日：2014-04-03
申请号：US13631288
申请日：2012-09-28
申请人： Prashant Dewan , Siddhartha Chhabra , Xiaozhu Kang , Xiaoning Li , Uday R. Savagaonkar , David M. Durham , Paul S. Schmitz , Michael A. Goldsmith , Jason Martin
发明人： Prashant Dewan , Siddhartha Chhabra , Xiaozhu Kang , Xiaoning Li , Uday R. Savagaonkar , David M. Durham , Paul S. Schmitz , Michael A. Goldsmith , Jason Martin
IPC分类号： G06F3/0481 , G06F3/041
CPC分类号： G06F3/0481 , G06F3/041 , G06F3/04883 , G06F21/74 , G06F21/82
摘要： A device and method for securely rendering content on a gesture-enabled computing device includes initializing a secure execution environment on a processor graphics of the computing device. The computing device transfers view rendering code and associated state data to the secure execution environment. An initial view of the content is rendered by executing the view rendering code in the secure execution environment. A gesture is recognized, and an updated view of the content is rendered in the secure execution environment in response to the gesture. The gesture may include a touch gesture recognized on a touch screen, or a physical gesture of the user recognized by a camera. After the updated view of the content is rendered, the main processor of the computing device may receive updated view data from the secure execution environment.
摘要翻译：用于在启用姿势的计算设备上安全地呈现内容的设备和方法包括在计算设备的处理器图形上初始化安全执行环境。计算设备将视图呈现代码和相关联的状态数据传送到安全执行环境。通过在安全执行环境中执行视图呈现代码来呈现内容的初始视图。识别手势，并且响应于手势在安全执行环境中呈现内容的更新视图。手势可以包括在触摸屏上识别的触摸手势，或者由相机识别的用户的身体手势。在呈现内容的更新视图之后，计算设备的主处理器可以从安全执行环境接收更新的视图数据。

8. 发明申请

US20100262739A1 IDENTIFIER ASSOCIATED WITH MEMORY LOCATIONS FOR MANAGING MEMORY ACCESSES 有权
标题翻译：与记忆管理存储器相关联的标识符
公开(公告)号：US20100262739A1
公开(公告)日：2010-10-14
申请号：US12824074
申请日：2010-06-25
申请人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
发明人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
IPC分类号： G06F12/00 , G06F13/24
CPC分类号： G06F12/1491
摘要： Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于将标识符与用于控制存储器访问的存储器位置相关联的装置，物品，方法和系统的实施例。可以描述和要求保护其他实施例。

9. 发明授权

US07761674B2 Identifier associated with memory locations for managing memory accesses 有权
标题翻译：与用于管理内存访问的内存位置相关联的标识符
公开(公告)号：US07761674B2
公开(公告)日：2010-07-20
申请号：US11322669
申请日：2005-12-30
申请人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
发明人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1491
摘要： Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于将标识符与用于控制存储器访问的存储器位置相关联的装置，物品，方法和系统的实施例。可以描述和要求保护其他实施例。

10. 发明申请

US20090327648A1 GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS 失效
标题翻译：每个虚拟机产生多个地址空间识别器，以保护受保护的微控制器
公开(公告)号：US20090327648A1
公开(公告)日：2009-12-31
申请号：US12165640
申请日：2008-06-30
申请人： Uday R. Savagaonkar , Madhaven Parthasarathy , Ravi Sahita , David Durham
发明人： Uday R. Savagaonkar , Madhaven Parthasarathy , Ravi Sahita , David Durham
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/145
摘要： Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage. The translation lookaside buffer is to store translations. Each translation lookaside buffer entry includes an address source identifiers. Each address source identifier is to identify a unique micro-context. Each address source identifier is based on a virtual partition identifier. At least two of the of virtual partition identifiers are associated with one of the virtual machines
摘要翻译：公开了用于在每个虚拟机之间生成多个地址空间标识符以在受保护的微上下文之间切换的发明的实施例。在一个实施例中，装置包括特权模式逻辑，接口和存储器管理逻辑。特权模式逻辑是在多个虚拟机之间传送处理器的控制。该接口是执行一个事务来从内存中获取信息。存储器管理逻辑将非翻译地址转换为存储器地址。存储器管理逻辑包括存储位置，一系列翻译级，确定逻辑和翻译后备缓冲器。存储位置是存储用于第一翻译阶段的数据结构的地址。每个翻译阶段包括翻译逻辑，以基于未翻译地址的一部分在数据结构中找到条目。每个条目是存储用于第一翻译阶段的不同数据结构的地址，用于连续翻译阶段的数据结构的地址或物理地址。确定逻辑是确定条目是否存储用于第一翻译阶段的不同数据结构的地址。翻译后备缓冲区用于存储翻译。每个翻译后备缓冲器条目包括地址源标识符。每个地址源标识符是识别唯一的微观上下文。每个地址源标识符都是基于虚拟分区标识符。至少两个虚拟分区标识符与一个虚拟机相关联

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