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1. 发明授权

US08407544B2 Method and apparatus for AC scan testing with distributed capture and shift logic 有权
标题翻译：用分布式捕获和移位逻辑进行交流扫描测试的方法和装置
公开(公告)号：US08407544B2
公开(公告)日：2013-03-26
申请号：US12761573
申请日：2010-04-16
申请人： Amitava Majumdar , Vasu Ganti
发明人： Amitava Majumdar , Vasu Ganti
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318552
摘要： An integrated circuit device includes a plurality of functional tiles. Each functional tile may be configured into a scan chain. A clock generator is operable to generate an internal clock signal that is distributed to each of the functional tiles. A clock gater is associated with each of the functional tiles. Each clock gater is operable to receive an external enable signal and the internal clock signal, generate a scan clock signal for loading a test pattern into the scan chain based on the external enable signal and the internal clock signal, and generate at least one capture clock signal for capturing a response of the tile to the test pattern responsive to identifying the loading of the test pattern.
摘要翻译：集成电路装置包括多个功能瓦片。每个功能瓦片可以被配置成扫描链。时钟发生器可操作以产生分配给每个功能瓦片的内部时钟信号。时钟门控器与每个功能瓦片相关联。每个时钟门控器可操作以接收外部使能信号和内部时钟信号，产生用于基于外部使能信号和内部时钟信号将测试图案加载到扫描链中的扫描时钟信号，并产生至少一个捕获时钟信号，用于响应于识别测试图案的加载而将瓦片的响应捕获到测试图案。

2. 发明申请

US20110258505A1 METHOD AND APPARATUS FOR AC SCAN TESTING WITH DISTRIBUTED CAPTURE AND SHIFT LOGIC 有权
标题翻译：用于分布式捕获和移动逻辑的交流扫描测试的方法和装置
公开(公告)号：US20110258505A1
公开(公告)日：2011-10-20
申请号：US12761573
申请日：2010-04-16
申请人： Amitava Majumdar , Vasu Ganti
发明人： Amitava Majumdar , Vasu Ganti
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318594 , G01R31/318552
摘要： An integrated circuit device includes a plurality of functional tiles. Each functional tile may be configured into a scan chain. A clock generator is operable to generate an internal clock signal that is distributed to each of the functional tiles. A clock gater is associated with each of the functional tiles. Each clock gater is operable to receive an external enable signal and the internal clock signal, generate a scan clock signal for loading a test pattern into the scan chain based on the external enable signal and the internal clock signal, and generate at least one capture clock signal for capturing a response of the tile to the test pattern responsive to identifying the loading of the test pattern.
摘要翻译：集成电路装置包括多个功能瓦片。每个功能瓦片可以被配置成扫描链。时钟发生器可操作以产生分配给每个功能瓦片的内部时钟信号。时钟门控器与每个功能瓦片相关联。每个时钟门控器可操作以接收外部使能信号和内部时钟信号，产生用于基于外部使能信号和内部时钟信号将测试图案加载到扫描链中的扫描时钟信号，并产生至少一个捕获时钟信号，用于响应于识别测试图案的加载而将瓦片的响应捕获到测试图案。

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