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    • 2. 发明授权
    • Test mode soft reset circuitry and methods
    • 测试模式软复位电路和方法
    • US07962819B2
    • 2011-06-14
    • US12019534
    • 2008-01-24
    • Baojing LiuMatt DavidsonVladimir Kovalev
    • Baojing LiuMatt DavidsonVladimir Kovalev
    • G01R31/28G06F11/00
    • G06F11/267G01R31/318555
    • An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.
    • 集成电路芯片包括扫描引脚,扫描时钟引脚和测试控制器。 扫描引脚和扫描时钟引脚接收测试模式类型和软复位模式的测试程序。 状态机被配置为直接对通过扫描时钟引脚提供的扫描时钟波形进行采样,如通过扫描引脚提供的扫描波形的转换所指示的。 执行软复位模式时,状态机从采样的扫描时钟波形中识别位匹配。 识别的位匹配触发软复位,在扫描模式下进行测试时,无需额外的复位引脚。
    • 3. 发明申请
    • TEST MODE SOFT RESET CIRCUITRY AND METHODS
    • 测试模式软复位电路和方法
    • US20090193305A1
    • 2009-07-30
    • US12019534
    • 2008-01-24
    • Baojing LiuMatt DavidsonVladimir Kovalev
    • Baojing LiuMatt DavidsonVladimir Kovalev
    • G01R31/28G06F11/25
    • G06F11/267G01R31/318555
    • An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to be executed, and the test controller accepting signals from the scan-in pin and the scan clock pin. The scan-in pin and the scan clock pin receiving a test program for the type of test mode and a soft-reset pattern. Also included is a state machine logic that is part of the integrated circuit chip. The state machine logic, during execution of the test program, being configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The sampling by the state machine circuitry identifying a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggering a soft reset by updating the test mode registers of the test controller. The soft reset therefore eliminates the need for an extra reset pin, when testing in scan mode. The communication channel defined through the use of the scan-in and scan clock pins can be used to trigger other soft actions.
    • 提供具有用于集成电路芯片的测试电路的测试逻辑的集成电路芯片。 集成电路芯片至少包括扫描引脚,扫描时钟引脚和测试控制器。 测试控制器具有用于存储要执行的测试模式类型的测试模式寄存器,并且测试控制器接受来自扫描引脚和扫描时钟引脚的信号。 扫描引脚和扫描时钟引脚接收测试模式类型的测试程序和软复位模式。 还包括作为集成电路芯片的一部分的状态机逻辑。 在执行测试程序期间,状态机逻辑被配置为直接通过扫描时钟引脚提供的扫描时钟波形的采样,如通过扫描引脚提供的扫描波形的转变所指示的。 在执行软复位模式时,由状态机电路进行采样,从采样的扫描时钟波形中识别位匹配。 所识别的位匹配通过更新测试控制器的测试模式寄存器来触发软复位。 因此,在扫描模式下进行测试时,软复位不需要额外的复位引脚。 通过使用扫描和扫描时钟引脚定义的通信通道可用于触发其他软操作。