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1. 发明申请

US20110093644A1 Memory Controller With Ring Bus for Interconnecting Memory Clients to Memory Devices 审中-公开
标题翻译：具有用于将内存客户端连接到内存设备的环形总线的内存控制器
公开(公告)号：US20110093644A1
公开(公告)日：2011-04-21
申请号：US12944660
申请日：2010-11-11
申请人： Warren F. Kruger , Patrick Law , Alexander Miretsky
发明人： Warren F. Kruger , Patrick Law , Alexander Miretsky
IPC分类号： G06F13/00 , G06F13/14
CPC分类号： G06F13/1657
摘要： Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic.
摘要翻译：描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个设备。环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。环形总线通过位于集成电路设备上的存储器件接口电路将物理上位于集成电路上的环形拓扑内的存储器客户端耦合到外部存储器件。存储器控制器还包括使用环形总线上的虚拟通道用于一个或多个定义类型的总线业务的死锁避免机制。

2. 发明申请

US20130159587A1 Interconnect Redundancy for Multi-Interconnect Device 审中-公开
标题翻译：多互连设备的互连冗余
公开(公告)号：US20130159587A1
公开(公告)日：2013-06-20
申请号：US13326663
申请日：2011-12-15
申请人： Aaron Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren F. Kruger
发明人： Aaron Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren F. Kruger
IPC分类号： G06F13/36
CPC分类号： G11C29/702 , G11C5/063
摘要： A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.
摘要翻译：多互连集成电路装置包括用于通过配置I / O电路来输送多个交错数据信道组的输入/输出（I / O）电路，以在默认的固定互连信号路径上传送第一数据信道组，如果在默认固定互连信号路径中没有连接故障，并且如果在第一多个默认固定互连信号路径中存在至少一个连接故障，并且在第二多个默认固定互连信号路径上传送第一数据信道组，其中所述第二多个默认固定互连信号路径包括用于从所述第一多个默认固定互连信号路径替换故障互连信号路径的冗余固定互连信号路径。

3. 发明授权

US08037281B2 Miss-under-miss processing and cache flushing 有权
标题翻译： Miss-under-miss处理和缓存刷新
公开(公告)号：US08037281B2
公开(公告)日：2011-10-11
申请号：US11889753
申请日：2007-08-16
申请人： Warren F. Kruger , Wade K. Smith
发明人： Warren F. Kruger , Wade K. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F9/30043 , G06F12/0862 , G06F2212/681 , G06F2212/684
摘要： Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.
摘要翻译：这里描述了减少当一级（L1）高速缓存向第二级（L2）高速缓存发出请求时可能发生的延迟的系统和方法，并且确保在上下文期间刷新发送到L2高速缓存的翻译请求开关。这样的系统可以包括工作队列和高速缓存（诸如L2高速缓存）。工作队列包括多个状态机，每个状态机被配置为存储访问存储器的请求。状态机可以监视存储在其他状态机中的请求，并请求其他状态机发出缓存。如果另一个状态机尚未等待与该请求有关的翻译数据，则状态机仅将其请求发送到缓存。以这种方式，工作队列和缓存之间的请求/转换流量可以大大减少。

4. 发明申请

US20080016254A1 Memory controller with ring bus for interconnecting memory clients to memory devices 有权
标题翻译：具有环形总线的内存控制器，用于将内存客户端连接到内存设备
公开(公告)号：US20080016254A1
公开(公告)日：2008-01-17
申请号：US11484191
申请日：2006-07-11
申请人： Warren F. Kruger , Patrick Law , Alexander Miretsky
发明人： Warren F. Kruger , Patrick Law , Alexander Miretsky
IPC分类号： G06F15/16
CPC分类号： G06F13/1657
摘要： Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic
摘要翻译：描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个设备。环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。环形总线通过位于集成电路设备上的存储器件接口电路将物理上位于集成电路上的环形拓扑内的存储器客户端耦合到外部存储器件。存储器控制器还包括使用环形总线上的虚拟通道用于一个或多个定义类型的总线业务的死锁避免机制

5. 发明授权

US08412912B2 Write data mask method and system 有权
标题翻译：写数据掩码的方法和系统
公开(公告)号：US08412912B2
公开(公告)日：2013-04-02
申请号：US13462502
申请日：2012-05-02
申请人： Xiaoling Xu , Warren F. Kruger
发明人： Xiaoling Xu , Warren F. Kruger
IPC分类号： G06F12/04
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1096
摘要： In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.
摘要翻译：在各种实施例中，通过在接口的地址线上发送数据掩码来消除专用掩码引脚。存储器控制器从存储器客户端接收对存储器写入操作的请求，并且根据客户端发送的写入数据掩码确定写入数据的粒度。如本文所使用的，粒度表示所接收的写数据掩码的每个位适用的写数据量。在一个实施例中，存储器控制器基于写入数据的粒度生成特定的写入命令和特定的写入数据掩码。所生成的写入命令通常是可用的多个写入命令中最有效的，但实施例不限于此。写命令在接口的命令行上传输，写数据掩码在接口的地址线上传输。

6. 发明授权

US07849256B2 Memory controller with ring bus for interconnecting memory clients to memory devices 有权
标题翻译：具有环形总线的内存控制器，用于将内存客户端连接到内存设备
公开(公告)号：US07849256B2
公开(公告)日：2010-12-07
申请号：US11484191
申请日：2006-07-11
申请人： Warren F. Kruger , Patrick Law , Alexander Miretsky
发明人： Warren F. Kruger , Patrick Law , Alexander Miretsky
IPC分类号： G06F13/37
CPC分类号： G06F13/1657
摘要： Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.
摘要翻译：描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个设备。环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。

7. 外观设计

USD559659S1 Grommet for a pallet 有权
标题翻译：垫圈用于托盘
公开(公告)号：USD559659S1
公开(公告)日：2008-01-15
申请号：US29249480
申请日：2006-10-09
申请人： Warren F. Kruger
设计人： Warren F. Kruger

8. 发明申请

US20120215996A1 WRITE DATA MASK METHOD AND SYSTEM 有权
标题翻译：写数据掩码方法和系统
公开(公告)号：US20120215996A1
公开(公告)日：2012-08-23
申请号：US13462502
申请日：2012-05-02
申请人： Xiaoling XU , Warren F. KRUGER
发明人： Xiaoling XU , Warren F. KRUGER
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1096
摘要： In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.
摘要翻译：在各种实施例中，通过在接口的地址线上发送数据掩码来消除专用掩码引脚。存储器控制器从存储器客户端接收对存储器写入操作的请求，并根据客户端发送的写入数据掩码确定写入数据的粒度。如本文所使用的，粒度表示所接收的写数据掩码的每个位适用的写数据量。在一个实施例中，存储器控制器基于写入数据的粒度生成特定的写入命令和特定的写入数据掩码。所生成的写入命令通常是可用的多个写入命令中最有效的，但实施例不限于此。写命令在接口的命令行上传输，写数据掩码在接口的地址线上传输。

9. 外观设计

USD557475S1 Pallet assembly 有权
标题翻译：托盘组装
公开(公告)号：USD557475S1
公开(公告)日：2007-12-11
申请号：US29248198
申请日：2006-08-02
申请人： Warren F. Kruger
设计人： Warren F. Kruger

10. 发明授权

US08275972B2 Write data mask method and system 有权
标题翻译：写数据掩码的方法和系统
公开(公告)号：US08275972B2
公开(公告)日：2012-09-25
申请号：US11509143
申请日：2006-08-23
申请人： Xiaoling Xu , Warren F. Kruger
发明人： Xiaoling Xu , Warren F. Kruger
IPC分类号： G06F12/04
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1096
摘要： In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.
摘要翻译：在各种实施例中，通过在接口的地址线上发送数据掩码来消除专用掩码引脚。存储器控制器从存储器客户端接收对存储器写入操作的请求，并且根据客户端发送的写入数据掩码确定写入数据的粒度。如本文所使用的，粒度表示所接收的写数据掩码的每个位适用的写数据量。在一个实施例中，存储器控制器基于写入数据的粒度生成特定的写入命令和特定的写入数据掩码。所生成的写入命令通常是可用的多个写入命令中最有效的，但实施例不限于此。写命令在接口的命令行上传输，写数据掩码在接口的地址线上传输。

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