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1. 发明授权

US10680797B2 Security-adaptive voltage conversion as a lightweight counter measure against LPA attacks 有权
公开(公告)号：US10680797B2
公开(公告)日：2020-06-09
申请号：US15967254
申请日：2018-04-30
申请人： Selcuk Kose , Weize Yu
发明人： Selcuk Kose , Weize Yu
IPC分类号： G06F21/00 , H04L9/00 , H04L9/06 , H03K19/00 , G06F21/75 , G06F21/60
摘要： Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.

2. 发明申请

US20180316488A1 FALSE KEY-CONTROLLED AGGRESSIVE VOLTAGE SCALING 审中-公开
公开(公告)号：US20180316488A1
公开(公告)日：2018-11-01
申请号：US15967171
申请日：2018-04-30
申请人： Selcuk Kose , Weize Yu
发明人： Selcuk Kose , Weize Yu
IPC分类号： H04L9/00 , G06F1/32 , H04L9/30 , G06F1/28
摘要： Methods and systems are provided for single false key-controlled (SFKC) aggressive voltage scaling (AVS) and multiple parallel false key controlled (MPFKC) AVS countermeasure systems. When a plaintext value is input into a cryptographic circuit for modification by a correct key, power supplied to the cryptographic circuit is scaled based on a result of the plaintext value modified by a false key or by a random number of parallel false keys, which occurs during every clock cycle. The scaling may be triggered when the operating frequency of the cryptographic circuit falls below a threshold, which indicates occurrence of a leakage power attack. A key that is detectable within a power trace of the scaled power provided to the cryptographic circuit, with a highest correlation coefficient relative to a known key, is a key other than the correct key. The MPFKC AVS technique also inhibits unriddling of the input power scaling scheme.

3. 发明申请

US20180314860A1 SYSTEM AND METHOD FOR SWITCHED-CAPACITOR BASED SIDE-CHANNEL COUNTERMEASURES 审中-公开
公开(公告)号：US20180314860A1
公开(公告)日：2018-11-01
申请号：US15967044
申请日：2018-04-30
申请人： Selcuk Kose , Weize Yu
发明人： Selcuk Kose , Weize Yu
IPC分类号： G06F21/75 , H02M3/07 , H04L9/00
CPC分类号： G06F21/755 , G06F7/582 , G06F21/556 , G06F21/81 , H02M3/07 , H04L9/003 , H04L9/0662 , H04L9/12
摘要： Methods and systems are provided for a charge withholding converter reshuffling technique that decorrelates input power of a multi-phase switched capacitor (SC) voltage converter relative to the output power provided to a load. The load may be a cryptographic device. The technique provides a countermeasure against power analysis attacks. A controller including a first random number generator coupled to the stages of the SC voltage converter controls gating for charging a first subset of the stages. A controller including a second random number generator coupled the stages of the SC voltage converter controls gating for discharging a second subset the stages. A number of the switched capacitor stages maintain their charge beyond the switch period in which they are charged. The SC voltage converter withholds a random portion of input charge and delivers this charge to the load after a random time period.

4. 发明申请

US20180316489A1 SECURITY-ADAPTIVE VOLTAGE CONVERSION AS A LIGHTWEIGHT COUNTER MEASURE AGAINST LPA ATTACKS 审中-公开
公开(公告)号：US20180316489A1
公开(公告)日：2018-11-01
申请号：US15967254
申请日：2018-04-30
申请人： Selcuk Kose , Weize Yu
发明人： Selcuk Kose , Weize Yu
IPC分类号： H04L9/00 , H04L9/06 , G06F21/60 , G06F21/75 , H03K19/00
CPC分类号： H04L9/003 , G06F21/602 , G06F21/755 , H03K19/0019 , H04L9/0618
摘要： Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.

5. 发明申请

US20140287565A1 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：制造半导体结构的方法
公开(公告)号：US20140287565A1
公开(公告)日：2014-09-25
申请号：US14354894
申请日：2011-12-02
申请人： Haizhou Yin , Weize Yu
发明人： Haizhou Yin , Weize Yu
IPC分类号： H01L29/66
CPC分类号： H01L29/66545 , H01L21/28 , H01L29/66575 , H01L29/78
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) providing a substrate (100); b) forming a dummy gate stack on the substrate (100), wherein the dummy gate stack consists of a gate dielectric layer (203) and a dummy gate (201) located on the gate dielectric layer (203), and the material of the dummy gate (201) is amorphous Si; c) performing ion implantation to regions exposed on both sides of the dummy gate (201) on the substrate (100), so as to form source/drain regions (110); d) forming an interlayer dielectric layer (400) that covers the source/drain regions (110) and the dummy gate stack; e) removing part of the interlayer dielectric layer (400) to expose the dummy gate (201) and removing the dummy gate (201); and f) annealing to activate dopants in source/drain regions. Procedures of the traditional gate-replacement process have been modified by the method for manufacturing a semiconductor structure provided by the present invention, thus etching period can be easily controlled, etching difficulty is alleviated, and stability of etching process is guaranteed as well.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括：a）提供衬底（100）; b）在所述衬底（100）上形成虚拟栅极堆叠，其中所述虚设栅极叠层由位于所述栅极介电层（203）上的栅极介电层（203）和伪栅极（201）组成，伪栅极（201）是非晶Si; c）对在衬底（100）上的伪栅极（201）的两侧露出的区域进行离子注入，以形成源/漏区（110）; d）形成覆盖源极/漏极区域（110）和虚拟栅极叠层的层间电介质层（400） e）去除所述层间介电层（400）的一部分以暴露所述虚拟栅极（201）并去除所述伪栅极（201）; 和f）退火以激活源/漏区中的掺杂剂。已经通过本发明提供的半导体结构的制造方法改进了传统的栅极替换工艺，因此可以容易地控制蚀刻时间，减轻蚀刻难度，并且保证蚀刻工艺的稳定性。

6. 发明申请

US20130277768A1 Semiconductor Structure And Method For Manufacturing The Same 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130277768A1
公开(公告)日：2013-10-24
申请号：US13816228
申请日：2011-12-01
申请人： Haizhou Yin , Weize Yu
发明人： Haizhou Yin , Weize Yu
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/28176 , H01L29/42368 , H01L29/513 , H01L29/518 , H01L29/66553 , H01L29/66575 , H01L29/78
摘要： The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises the following steps: providing a substrate and forming a sacrificial gate, sidewall spacers and source/drain regions located on both sides of the sacrificial gate; forming an interlayer dielectric layer that covers the device; removing the sacrificial gate to form a cavity within the sidewall spacers; forming first oxygen absorbing layers in the cavity; forming a second oxygen absorbing layer in the remaining of the space of the cavity; and performing an annealing step to make the surface of the substrate form an interfacial layer. The present invention further provides a semiconductor structure. By forming a symmetrical interfacial layer in a channel region, the present invention has reduced processing difficulty while effectively mitigating short-channel effects and preserving carrier mobility.
摘要翻译：本发明提供半导体结构及其制造方法。该方法包括以下步骤：提供衬底并形成位于牺牲栅极两侧的牺牲栅极，侧壁间隔物和源极/漏极区域; 形成覆盖所述器件的层间电介质层; 去除所述牺牲栅极以在所述侧壁间隔件内形成空腔; 在空腔中形成第一氧吸收层; 在空腔的剩余部分中形成第二氧吸收层; 并进行退火步骤以使基材的表面形成界面层。本发明还提供一种半导体结构。通过在通道区域中形成对称的界面层，本发明降低了处理难度，同时有效地减轻了短沟道效应并保持了载流子迁移率。

7. 发明授权

US10691836B2 System and method for switched-capacitor based side-channel countermeasures 有权
公开(公告)号：US10691836B2
公开(公告)日：2020-06-23
申请号：US15967044
申请日：2018-04-30
申请人： Selcuk Kose , Weize Yu
发明人： Selcuk Kose , Weize Yu
IPC分类号： G06F21/75 , H04L9/00 , H02M3/07 , G06F21/81 , G06F21/55 , H04L9/12 , H04L9/06 , G06F7/58
摘要： Methods and systems are provided for a charge withholding converter reshuffling technique that decorrelates input power of a multi-phase switched capacitor (SC) voltage converter relative to the output power provided to a load. The load may be a cryptographic device. The technique provides a countermeasure against power analysis attacks. A controller including a first random number generator coupled to the stages of the SC voltage converter controls gating for charging a first subset of the stages. A controller including a second random number generator coupled the stages of the SC voltage converter controls gating for discharging a second subset the stages. A number of the switched capacitor stages maintain their charge beyond the switch period in which they are charged. The SC voltage converter withholds a random portion of input charge and delivers this charge to the load after a random time period.

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