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1. 发明授权

US09390949B2 Wafer debonding and cleaning apparatus and method of use 有权
标题翻译：晶圆剥离和清洗装置及其使用方法
公开(公告)号：US09390949B2
公开(公告)日：2016-07-12
申请号：US13306625
申请日：2011-11-29
申请人： Wen-Chih Chiou , Yu-Liang Lin , Hung-Jung Tu
发明人： Wen-Chih Chiou , Yu-Liang Lin , Hung-Jung Tu
IPC分类号： H01L21/02 , H01L21/677 , H01L21/67
CPC分类号： H01L21/67173 , H01L21/02057 , H01L21/67207
摘要： This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a semiconductor wafer into a wafer debonding module for a debonding process. The automatic wafer handling module removes the semiconductor wafer from the debonding module and loads the semiconductor wafer into a wafer cleaning module for a cleaning process.
摘要翻译：本说明书涉及包括自动晶片处理模块的晶片剥离和清洁设备。自动晶片处理模块将半导体晶片加载到用于脱粘工艺的晶片剥离模块中。自动晶片处理模块从剥离模块中移除半导体晶片，并将半导体晶片装载到用于清洁过程的晶片清洁模块中。

2. 发明授权

US09153462B2 Spin chuck for thin wafer cleaning 有权
标题翻译：旋转夹头用于薄晶圆清洗
公开(公告)号：US09153462B2
公开(公告)日：2015-10-06
申请号：US12964097
申请日：2010-12-09
申请人： Yu-Liang Lin , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou
发明人： Yu-Liang Lin , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou
IPC分类号： H01L21/687 , H01L21/67
CPC分类号： H01L21/67051 , H01L21/68728
摘要： A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.
摘要翻译：公开了用于薄晶片清洁的装置和系统。优选实施例包括具有至少三个保持夹具的旋转卡盘。具有晶片框架的薄晶片通过带层安装在旋转卡盘上。当保持夹具解锁时，不会干扰晶片框架的移除和放置。另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

3. 发明授权

US08896136B2 Alignment mark and method of formation 有权
标题翻译：对齐标记和形成方法
公开(公告)号：US08896136B2
公开(公告)日：2014-11-25
申请号：US12827563
申请日：2010-06-30
申请人： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L29/40 , H01L23/48 , H01L23/52 , H01L21/76 , H01L21/00 , H01L21/4763 , H01L21/44 , H01L21/683
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/6835 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2224/13
摘要： In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
摘要翻译：根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

4. 发明授权

US08847388B2 Bump with protection structure 有权
标题翻译：有保护结构的凹凸
公开(公告)号：US08847388B2
公开(公告)日：2014-09-30
申请号：US13267200
申请日：2011-10-06
申请人： Chen-Hua Yu , Hung-Pin Chang , An-Jhih Su , Tsang-Jiuh Wu , Wen-Chih Chiou , Shin-Puu Jeng
发明人： Chen-Hua Yu , Hung-Pin Chang , An-Jhih Su , Tsang-Jiuh Wu , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号： H01L23/48 , H01L23/31 , H01L23/00 , H01L23/29
CPC分类号： H01L23/293 , H01L23/3192 , H01L24/01 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05571 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10126 , H01L2224/11334 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13007 , H01L2224/13018 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/15788 , H01L2924/014 , H01L2924/00012 , H01L2924/04941 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.
摘要翻译：半导体器件包括形成在钝化后互连（PPI）线上并由保护结构包围的凸块结构。保护结构包括聚合物层和至少一个电介质层。电介质层可以形成在聚合物层的顶表面上，该聚合物层的下面，插入凸起结构和聚合物层之间，插入在PPI线和聚合物层之间，覆盖聚合物层的外侧壁，或其组合。

5. 发明授权

US08846499B2 Composite carrier structure 有权
标题翻译：复合载体结构
公开(公告)号：US08846499B2
公开(公告)日：2014-09-30
申请号：US12858211
申请日：2010-08-17
申请人： Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L21/30
CPC分类号： G07F17/3213 , B32B17/10 , B32B37/1207 , B32B37/182 , B32B37/185 , B32B2457/14 , H01L21/6835 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要： A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.
摘要翻译：提供了一种用于制造半导体器件的复合载体结构。复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

6. 发明授权

US08815618B2 Light-emitting diode on a conductive substrate 有权
标题翻译：导电基板上的发光二极管
公开(公告)号：US08815618B2
公开(公告)日：2014-08-26
申请号：US12541787
申请日：2009-08-14
申请人： Ding-Yuan Chen , Chen-Hua Yu , Wen-Chih Chiou
发明人： Ding-Yuan Chen , Chen-Hua Yu , Wen-Chih Chiou
IPC分类号： H01L33/00 , H01L21/78
CPC分类号： H01L33/0062 , H01L21/78 , H01L33/0066 , H01L33/0079 , H01L2924/01078 , H01S5/1231 , H01S5/2275
摘要： A light-emitting diode (LED) device is provided. The LED device is formed by forming an LED structure on a first substrate. A portion of the first substrate is converted to a porous layer, and a conductive substrate is formed over the LED structure on an opposing surface from the first substrate. The first substrate is detached from the LED structure along the porous layer and any remaining materials are removed from the LED structure.
摘要翻译：提供了一种发光二极管（LED）装置。 LED器件通过在第一衬底上形成LED结构而形成。将第一衬底的一部分转换成多孔层，并且在与第一衬底相对的表面上的LED结构上形成导电衬底。第一衬底沿着多孔层与LED结构分离，并且从LED结构中去除任何剩余的材料。

7. 发明授权

US08791549B2 Wafer backside interconnect structure connected to TSVs 有权
标题翻译：晶圆背面互连结构连接到TSV
公开(公告)号：US08791549B2
公开(公告)日：2014-07-29
申请号：US12832019
申请日：2010-07-07
申请人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
发明人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L24/81 , H01L21/76807 , H01L21/76813 , H01L21/76816 , H01L21/76841 , H01L21/76843 , H01L21/76877 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05025 , H01L2224/05546 , H01L2224/05547 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2224/13155 , H01L2224/14181 , H01L2224/811 , H01L2224/8136 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
摘要翻译：集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。金属线包括双镶嵌结构。集成电路结构还包括覆盖金属线的凸块。

8. 发明授权

US08742441B2 Light-emitting diode with embedded elements 有权
标题翻译：具有嵌入元件的发光二极管
公开(公告)号：US08742441B2
公开(公告)日：2014-06-03
申请号：US12547428
申请日：2009-08-25
申请人： Ding-Yuan Chen , Wen-Chih Chiou , Chen-Hua Yu
发明人： Ding-Yuan Chen , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L29/72
CPC分类号： H01L33/44 , H01L33/08 , H01L33/20
摘要： A light-emitting diode (LED) device is provided. The LED device has a substrate and an LED structure overlying the substrate. Embedded elements are embedded within one or more layers of the LED structure. In an embodiment, the embedded elements include a dielectric material extending through the LED structure such that the embedded elements are surrounded by the LED structure. In another embodiment, the embedded elements only extend through an upper layer of the LED structure, or alternatively, partially through the upper layer of the LED structure. Another conductive layer may be formed over the upper layer of the LED structure and the embedded elements.
摘要翻译：提供了一种发光二极管（LED）装置。 LED器件具有衬底和覆盖衬底的LED结构。嵌入式元件嵌入LED结构的一层或多层内。在一个实施例中，嵌入元件包括延伸穿过LED结构的电介质材料，使得嵌入元件被LED结构包围。在另一个实施例中，嵌入式元件仅延伸穿过LED结构的上层，或者部分地穿过LED结构的上层。另外的导电层可以形成在LED结构的上层和嵌入元件上。

9. 发明授权

US08691706B2 Reducing substrate warpage in semiconductor processing 有权
标题翻译：降低半导体加工中的基板翘曲
公开(公告)号：US08691706B2
公开(公告)日：2014-04-08
申请号：US13349323
申请日：2012-01-12
申请人： Chen-Hua Yu , Wen-Chih Chiou , Fang Wen Tsai , Kuang-Wei Cheng , Jiann Sheng Chang , Yi Chou Lai , Jiung Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Fang Wen Tsai , Kuang-Wei Cheng , Jiann Sheng Chang , Yi Chou Lai , Jiung Wu
IPC分类号： H01L21/02
CPC分类号： C23C16/0209 , H01L21/67115 , H01L21/67201 , H01L21/67288
摘要： System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
摘要翻译：用于减少热过程中的基板翘曲的系统和方法。一个实施例包括在执行衬底的热处理之前预先加载负载锁定室中的衬底。在热处理之后，基板在负载锁定室中被冷却。预热和冷却过程减少了由构成基材的材料的热膨胀系数（CTE）所引起的基板翘曲。

10. 发明授权

US08629568B2 Semiconductor device cover mark 有权
标题翻译：半导体器件盖标记
公开(公告)号：US08629568B2
公开(公告)日：2014-01-14
申请号：US12847802
申请日：2010-07-30
申请人： Yan-Fu Lin , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Yan-Fu Lin , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L21/563 , H01L23/49838 , H01L23/544 , H01L24/11 , H01L24/81 , H01L2223/54413 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/73204 , H01L2224/8113 , H01L2224/81132 , H01L2224/81191 , H01L2224/81815 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.
摘要翻译：提供了一种用于确定底部填充膨胀的系统和方法。一个实施例包括沿着衬底的顶表面形成覆盖标记，将半导体衬底附接到衬底的顶表面，将底部填充材料放置在半导体衬底和衬底之间，然后使用覆盖标记来确定底部填充在基材的顶表面上。此外，也可以沿着半导体衬底的顶表面形成覆盖标记，并且衬底和半导体衬底上的覆盖标记可以在衬底和半导体衬底的对准期间一起用作对准标记。

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