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1. 发明授权

US08330514B2 One-shot circuit capable of being integrated into a chip, transmitter capable of reducing start-up time, and related method 有权
标题翻译：能够集成到芯片中的单触发电路，能够减少启动时间的发送器以及相关方法
公开(公告)号：US08330514B2
公开(公告)日：2012-12-11
申请号：US13102063
申请日：2011-05-06
申请人： Wen-Jan Lee
发明人： Wen-Jan Lee
IPC分类号： H03L7/06
CPC分类号： H03K21/38 , G06F1/04
摘要： A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.
摘要翻译：能够集成到芯片中的单触发电路根据时钟信号发生器的参考时钟信号通过分频电路产生分频信号。以这种方式，可以通过增加分频电路中的分频时间来提高分频信号的周期长度的大小的顺序，使得RC振荡器的电阻和电容时钟信号发生器有效降低。因此，由时钟信号发生器的RC振荡器所占用的电路面积减小，使得单片电路可以集成到芯片中而不增加成本。

2. 发明申请

US20110273209A1 One-shot circuit capable of being integrated into a chip, transmitter capable of reducing start-up time, and related method 有权
标题翻译：能够集成到芯片中的单触发电路，能够减少启动时间的发送器以及相关方法
公开(公告)号：US20110273209A1
公开(公告)日：2011-11-10
申请号：US13102063
申请日：2011-05-06
申请人： Wen-Jan Lee
发明人： Wen-Jan Lee
IPC分类号： H03L7/06 , H03K21/38
CPC分类号： H03K21/38 , G06F1/04
摘要： A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.
摘要翻译：能够集成到芯片中的单触发电路根据时钟信号发生器的参考时钟信号通过分频电路产生分频信号。以这种方式，可以通过增加分频电路中的分频时间来提高分频信号的周期长度的大小的顺序，使得RC振荡器的电阻和电容时钟信号发生器有效降低。因此，由时钟信号发生器的RC振荡器所占用的电路面积减小，使得单片电路可以集成到芯片中而不增加成本。

3. 发明申请

US20080191775A1 Baseline wandering correction device and related method 失效
标题翻译：基线游荡矫正装置及相关方法
公开(公告)号：US20080191775A1
公开(公告)日：2008-08-14
申请号：US11889151
申请日：2007-08-09
申请人： Wen-Jan Lee
发明人： Wen-Jan Lee
IPC分类号： H04L25/02 , H04L25/06
CPC分类号： H04L25/061 , H04L25/063
摘要： The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated signal, an extracting module coupling to the operation module and determining a first and a second threshold value according to the operated signal, a comparing signal coupling to the extracting module and comparing the operated signal with the first and second threshold values to generate a first and a second processing signal, and a latch module latching the first and second processing signals to generate an output signal.
摘要翻译：本发明公开了基线漂移校正技术。基线漂移校正装置包括区分数据信号以产生微分信号的微分器，耦合到微分器的操作信号，并且根据差分信号基于数据信号进行操作以产生操作信号，提取模块耦合根据所操作的信号确定第一和第二阈值;比较信号，其耦合到所述提取模块，并将所操作的信号与所述第一和第二阈值进行比较，以生成第一和第二处理信号;以及锁存模块，其锁存第一和第二处理信号以产生输出信号。

4. 发明授权

US07933358B2 GFSK/FSK modulation circuit and related method implemented in a digital manner 有权
标题翻译： GFSK / FSK调制电路及相关方法以数字方式实现
公开(公告)号：US07933358B2
公开(公告)日：2011-04-26
申请号：US11563688
申请日：2006-11-28
申请人： Kwo-Wei Chang , Wen-Jan Lee
发明人： Kwo-Wei Chang , Wen-Jan Lee
IPC分类号： H03C3/00
CPC分类号： H04L27/122
摘要： A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.
摘要翻译：以数字方式实现的高斯频移键控/频移键控（GFSK / FSK）调制电路包括用于分频输入时钟信号的频率以获得采样信号的分频器，连接到分频器的用于存储输入数据的缓冲器耦合到缓冲器的积分器，用于根据从缓冲器输出的数据进行积分处理;耦合到积分器的第一只读存储器，用于根据余弦函数传送从积分器输出的数据;以及第二只读存储器，耦合到积分器，用于根据正弦函数传送从积分器输出的数据。

5. 发明申请

US20070229174A1 CALIBRATION LOOP, FILTER CIRCUIT AND RELATED METHOD CAPABLE OF AUTOMATICALLY ADJUSTING CENTER FREQUENCY OF A FILTER 审中-公开
标题翻译：校准环，滤波电路及相关方法可自动调节滤波器的中心频率
公开(公告)号：US20070229174A1
公开(公告)日：2007-10-04
申请号：US11562991
申请日：2006-11-23
申请人： Kwo-Wei Chang , Chun-Yi Li , Wen-Jan Lee
发明人： Kwo-Wei Chang , Chun-Yi Li , Wen-Jan Lee
IPC分类号： H03L7/00
CPC分类号： H03H11/0472 , H03H11/0444 , H03H2011/0494 , H03H2210/012 , H03H2210/023
摘要： A calibration loop includes an oscillator, an integrator, an amplitude comparator, and a working voltage adjuster. The oscillator is used for generating a reference clock signal. The integrator is coupled to the oscillator for generating an output amplitude according to the reference clock signal and a working voltage. The first input end of the amplitude comparator is coupled to the integrator and the second input end of the amplitude comparator is coupled to the oscillator. The amplitude comparator is used for comparing the output amplitude of the integrator with an amplitude of the reference clock signal of the oscillator and outputting a comparison result. The input end of the working voltage adjuster is coupled to the amplitude comparator, and the output end of the working voltage adjuster is coupled to the integrator. The working voltage adjuster is used for tuning the input working voltage according to the comparison result.
摘要翻译：校准回路包括振荡器，积分器，幅度比较器和工作电压调节器。振荡器用于产生参考时钟信号。积分器耦合到振荡器，用于根据参考时钟信号和工作电压产生输出幅度。振幅比较器的第一输入端耦合到积分器，并且振幅比较器的第二输入端耦合到振荡器。振幅比较器用于将积分器的输出幅度与振荡器的参考时钟信号的振幅进行比较，并输出比较结果。工作电压调节器的输入端耦合到幅度比较器，工作电压调节器的输出端耦合到积分器。工作电压调节器用于根据比较结果对输入工作电压进行调谐。

6. 发明申请

US20070211825A1 GFSK/FSK Modulation Circuit and Related Method Implemented in A Digital Manner 有权
标题翻译： GFSK / FSK调制电路及相关方法以数字方式实现
公开(公告)号：US20070211825A1
公开(公告)日：2007-09-13
申请号：US11563688
申请日：2006-11-28
申请人： Kwo-Wei Chang , Wen-Jan Lee
发明人： Kwo-Wei Chang , Wen-Jan Lee
IPC分类号： H04L27/12
CPC分类号： H04L27/122
摘要： A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.
摘要翻译：以数字方式实现的高斯频移键控/频移键控（GFSK / FSK）调制电路包括用于分频输入时钟信号的频率以获得采样信号的分频器，连接到分频器的用于存储输入数据的缓冲器耦合到缓冲器的积分器，用于根据从缓冲器输出的数据进行积分处理;耦合到积分器的第一只读存储器，用于根据余弦函数传送从积分器输出的数据;以及第二只读存储器，耦合到积分器，用于根据正弦函数传送从积分器输出的数据。

7. 发明授权

US07541856B2 Baseline wandering correction device and related method 失效
标题翻译：基线游荡矫正装置及相关方法
公开(公告)号：US07541856B2
公开(公告)日：2009-06-02
申请号：US11889151
申请日：2007-08-09
申请人： Wen-Jan Lee
发明人： Wen-Jan Lee
IPC分类号： H03L5/00
CPC分类号： H04L25/061 , H04L25/063
摘要： The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated signal, an extracting module coupling to the operation module and determining a first and a second threshold value according to the operated signal, a comparing signal coupling to the extracting module and comparing the operated signal with the first and second threshold values to generate a first and a second processing signal, and a latch module latching the first and second processing signals to generate an output signal.
摘要翻译：本发明公开了基线漂移校正技术。基线漂移校正装置包括区分数据信号以产生微分信号的微分器，耦合到微分器的操作信号，并且根据差分信号基于数据信号进行操作以产生操作信号，提取模块耦合根据所操作的信号确定第一和第二阈值;比较信号，其耦合到所述提取模块，并将所操作的信号与所述第一和第二阈值进行比较，以生成第一和第二处理信号;以及锁存模块，其锁存第一和第二处理信号以产生输出信号。

8. 发明申请

US20070160174A1 Packet preamble search method and device thereof 有权
标题翻译：分组前同步码搜索方法及其装置
公开(公告)号：US20070160174A1
公开(公告)日：2007-07-12
申请号：US11478767
申请日：2006-07-03
申请人： Jia-Yu Yang , Wen-Jan Lee , Kwo-Wei Chang
发明人： Jia-Yu Yang , Wen-Jan Lee , Kwo-Wei Chang
IPC分类号： H04L7/00
CPC分类号： H04L7/042
摘要： A packet preamble search method for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.
摘要翻译：一种分组前同步码搜索方法，用于在具有顺序多个模式的接收的传输信号内定位具有规则形式的多个预定模式的分组前导码。所接收的发送信号的模式和分组前导码的预定模式具有与偶数比特相同的长度。顺序地将发送信号的模式与预定模式进行比较。当发送信号的模式与预定模式匹配时，命中计数增加，并且忽略计数被复位。当发送信号的模式与预定模式不匹配时，小数计数增加并且命中数减少。当命中数小于或等于错过次数时，命中计数和未命中计数将被重置。当命中数超过或等于阈值时，地址匹配过程被激活。

9. 发明授权

US07792233B2 Packet preamble search method and device thereof 有权
标题翻译：分组前同步码搜索方法及其装置
公开(公告)号：US07792233B2
公开(公告)日：2010-09-07
申请号：US11478767
申请日：2006-07-03
申请人： Jia-Yu Yang , Wen-Jan Lee , Kwo-Wei Chang
发明人： Jia-Yu Yang , Wen-Jan Lee , Kwo-Wei Chang
IPC分类号： H04L7/00
CPC分类号： H04L7/042
摘要： A packet preamble search method is disclosed for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.
摘要翻译：公开了一种分组前导码搜索方法，用于在具有顺序多个模式的接收的传输信号内定位具有规则形式的多个预定模式的分组前导码。所接收的发送信号的模式和分组前导码的预定模式具有与偶数比特相同的长度。顺序地将发送信号的模式与预定模式进行比较。当发送信号的模式与预定模式匹配时，命中计数增加，并且忽略计数被复位。当发送信号的模式与预定模式不匹配时，小数计数增加并且命中数减少。当命中数小于或等于错过次数时，命中计数和未命中计数将被重置。当命中数超过或等于阈值时，地址匹配过程被激活。

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