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1. 发明授权

US08018704B2 Parallel analog and digital timers in power controller circuit breaker 有权
标题翻译：电源控制器断路器中的并行模拟和数字定时器
公开(公告)号：US08018704B2
公开(公告)日：2011-09-13
申请号：US11466741
申请日：2006-08-23
申请人： William Andrew Burkland , Adolfo A. Garcia
发明人： William Andrew Burkland , Adolfo A. Garcia
IPC分类号： H02H3/05
CPC分类号： H02H3/087 , H02H9/025
摘要： A circuit breaker for a power controller integrated circuit is described where an analog timer and a digital timer are provided in parallel. The digital timer provides a fixed, on-chip maximum delay during an overcurrent condition to ensure the transistor will not be damaged. The analog timer allows the user to select an external capacitor or resistor to provide a delay time that is shorter than the time provided by the digital timer. Accordingly, the power controller retains all the flexibility of an analog timer but prevents the overcurrent exceeding a maximum time limit. An autoretry circuit is also included in the power controller which prevents the duty cycle from exceeding a maximum. The autoretry timer is a digital timer that uses the same oscillator as the digital timer for the circuit breaker so the ratio of the delay times is known and fixed.
摘要翻译：描述了并联提供模拟定时器和数字定时器的用于功率控制器集成电路的断路器。数字定时器在过流条件下提供固定的片内最大延迟，以确保晶体管不会损坏。模拟定时器允许用户选择一个外部电容或电阻来提供比数字定时器提供的时间短的延迟时间。因此，功率控制器保持模拟定时器的所有灵活性，但是防止过电流超过最大时限。电源控制器中还包括一个自动重合电路，可防止占空比超过最大值。自动重试定时器是一个数字定时器，它使用与断路器数字定时器相同的振荡器，因此延迟时间的比例是已知和固定的。

2. 发明授权

US07624303B2 Generation of system power-good signal in hot-swap power controllers 有权
标题翻译：在热插拔电源控制器中产生系统电源良好信号
公开(公告)号：US07624303B2
公开(公告)日：2009-11-24
申请号：US11466731
申请日：2006-08-23
申请人： William Andrew Burkland , Adolfo A. Garcia
发明人： William Andrew Burkland , Adolfo A. Garcia
IPC分类号： G06F11/00
CPC分类号： G06F1/30
摘要： A power controller system is described herein, which may consist of one or more power controller ICs and other components. Each power controller selectively couples power supply voltages to a plurality of electrical devices, such as cards that have been inserted into expansion slots in a server. To simplify processing by a system processor monitoring the health of the power subsystem, each power controller IC asserts a power-good signal at a power-good terminal only if the operating conditions for all channels are satisfactory. A power good signal is generated even if a channel is not supplying power to a channel due to a card retention switch signal not being asserted or the channel is not enabled. The power-good signals from all power controllers in the system are then ANDed together to determine if any of the power controllers are experiencing unsatisfactory conditions. If the resulting single signal is an asserted power-good signal, then the system knows that all channels in all the power controllers are experiencing satisfactory conditions, even though some channels may not be enabled or there are no modules (e.g., cards) connected to a power controller.
摘要翻译：这里描述了功率控制器系统，其可以由一个或多个功率控制器IC和其它组件组成。每个功率控制器选择性地将电源电压耦合到多个电气设备，例如已经插入服务器中的扩展槽中的卡。为了简化系统处理器监控电源子系统健康状况的处理，每个功率控制器IC只有在所有通道的工作条件都令人满意的情况下，才能在电源良好端口断言电源良好信号。即使由于卡保持开关信号未被断言或通道未被使能而导致通道不向通道供电，也会产生电源良好信号。然后，将系统中所有电源控制器的电源良好信号进行AND运算，以确定是否有任何电源控制器遇到不令人满意的状况。如果所得到的单个信号是断言的功率良好信号，则系统知道所有功率控制器中的所有通道正在经历令人满意的条件，即使某些通道可能未启用或没有模块（例如，卡）连接到电源控制器

3. 发明授权

US07292084B2 Timer circuit with adaptive reference 有权
标题翻译：定时器电路具有自适应参考
公开(公告)号：US07292084B2
公开(公告)日：2007-11-06
申请号：US11457284
申请日：2006-07-13
申请人： Boris Briskin , William Andrew Burkland
发明人： Boris Briskin , William Andrew Burkland
IPC分类号： H03H11/26
CPC分类号： H03K5/153 , H03K5/13 , H03K2005/00104 , H03K2005/00156 , H03K2005/00202
摘要： A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The capacitor receives the first current as a sinking current or as a sourcing current. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage.
摘要翻译：定时器电路包括电流镜，电容器，第一开关，电阻器和比较器。电流镜接收参考电流并且提供具有预定电流比的第一和第二电流。电容器接收第一电流作为吸收电流或作为源电流。由控制信号控制的第一开关允许电容器由第一电流充电或放电。电阻器被第二电流偏置以提供自适应参考电压。比较器比较电容器两端的电压和自适应参考电压，并在电容电压增加到自适应参考电压时触发输出信号。

4. 发明授权

US07865754B2 Power budget management in power over ethernet systems 有权
标题翻译：对以太网系统供电的电力预算管理
公开(公告)号：US07865754B2
公开(公告)日：2011-01-04
申请号：US11865966
申请日：2007-10-02
申请人： William Andrew Burkland , Douglas Paul Anderson
发明人： William Andrew Burkland , Douglas Paul Anderson
IPC分类号： G06F1/00
CPC分类号： H04L12/10
摘要： A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node into a monitor current. The second resistor has a resistance value proportional to a maximum power budget of the PSE and receives the monitor current. A monitor voltage develops across the second resistor indicative of the total power demanded by the power ports. The comparator compares the monitor voltage to the reference voltage and provides a comparator output signal indicating whether the maximum power budget of the PSE has been exceeded.
摘要翻译：多端口PSE中的功率预算监控电路包括差分放大器和用于设置第一电阻器两端的参考电压以建立参考电流的晶体管，每个与PSE的电源端口相关联的多个电流镜输出装置，第二电阻和比较器。每个电流镜输出装置提供指示由相关电力端口所要求的功率的输出电流，其中输出电流在第二节点处相加到监视电流中。第二电阻具有与PSE的最大功率预算成比例的电阻值，并接收监视电流。在第二电阻器上形成监测电压，指示电力端口所需的总功率。比较器将监视电压与参考电压进行比较，并提供一个比较器输出信号，指示是否超过了PSE的最大功率预算。

5. 发明申请

US20080055808A1 Parallel Analog and Digital Timers in Power Controller Circuit Breaker 有权
标题翻译：并联模拟和数字定时器在电源控制器断路器
公开(公告)号：US20080055808A1
公开(公告)日：2008-03-06
申请号：US11466741
申请日：2006-08-23
申请人： William Andrew Burkland , Adolfo A. Garcia
发明人： William Andrew Burkland , Adolfo A. Garcia
IPC分类号： H02H3/00
CPC分类号： H02H3/087 , H02H9/025
摘要： A circuit breaker for a power controller integrated circuit is described where an analog timer and a digital timer are provided in parallel. The digital timer provides a fixed, on-chip maximum delay during an overcurrent condition to ensure the transistor will not be damaged. The analog timer allows the user to select an external capacitor or resistor to provide a delay time that is shorter than the time provided by the digital timer. Accordingly, the power controller retains all the flexibility of an analog timer but prevents the overcurrent exceeding a maximum time limit. An autoretry circuit is also included in the power controller which prevents the duty cycle from exceeding a maximum. The autoretry timer is a digital timer that uses the same oscillator as the digital timer for the circuit breaker so the ratio of the delay times is known fixed.
摘要翻译：描述了并联提供模拟定时器和数字定时器的用于功率控制器集成电路的断路器。数字定时器在过流条件下提供固定的片内最大延迟，以确保晶体管不会损坏。模拟定时器允许用户选择一个外部电容或电阻来提供比数字定时器提供的时间短的延迟时间。因此，功率控制器保持模拟定时器的所有灵活性，但是防止过电流超过最大时限。电源控制器中还包括一个自动重合电路，可防止占空比超过最大值。自动重试定时器是数字定时器，它使用与断路器数字定时器相同的振荡器，因此延迟时间的比例已知是固定的。

6. 发明授权

US07138843B2 Timer circuit with adaptive reference 有权
公开(公告)号：US07138843B2
公开(公告)日：2006-11-21
申请号：US10968701
申请日：2004-10-18
申请人： Boris Briskin , William Andrew Burkland
发明人： Boris Briskin , William Andrew Burkland
IPC分类号： H03H11/26
CPC分类号： H03K5/153 , H03K5/13 , H03K2005/00104 , H03K2005/00156 , H03K2005/00202
摘要： A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.

7. 发明授权

US06734704B1 Voltage level-shifting control circuit for electronic switch 有权
标题翻译：电子开关电压电平转换控制电路
公开(公告)号：US06734704B1
公开(公告)日：2004-05-11
申请号：US10040540
申请日：2001-12-28
申请人： William Andrew Burkland
发明人： William Andrew Burkland
IPC分类号： H03K190175
CPC分类号： H03K17/04163 , H03K17/063 , H03K17/6871 , H03K19/018571
摘要： A control circuit receives complementary logic signals ranging from Vdd to 0 VDC, and outputs a drive signal Vhs1 ranging from magnitude Vhv to Vhv+Vdd to control a high-side switch. The control circuit includes an Ibias generator and a level shift circuit that preferably includes a passive current sink mechanism, coupleable between Vdd and ground. The level shift circuit includes a totem-pole configuration of a PMOS device, an NMOS device, and an NMOS device that mirrors Ibias current. An additional NMOS device is provided, whose source node is coupled between the PMOS and NMOS devices in the totem-pole, whose gate node is coupled to Vdd, and whose drain node serves as an interface to the load circuit. A capacitor coupled across the current source hastens Vhs1 transition time. The PMOS and NMOS devices in the totem pole turn on and off complementarily responsive to the logic signals, which dictate the state of Vhs1.
摘要翻译：控制电路接收范围从Vdd到0VDC的互补逻辑信号，并输出范围从Vhv到Vhv + Vdd的驱动信号Vhs1以控制高侧开关。控制电路包括Ibias发生器和电平移位电路，其优选地包括可在Vdd和地之间耦合的无源电流吸收机构。电平移位电路包括PMOS器件的图腾柱结构，NMOS器件和反映Ibias电流的NMOS器件。提供了一个额外的NMOS器件，其源极节点耦合在图腾柱中的PMOS和NMOS器件之间，其栅极节点耦合到Vdd，其漏极节点用作与负载电路的接口。耦合在电流源上的电容加速Vhs1转换时间。图腾柱中的PMOS和NMOS器件对逻辑信号进行互补响应，这些逻辑信号决定了Vhs1的状态。

8. 发明授权

US07203213B2 Laser turn-on accelerator independent of bias control loop bandwidth 有权
标题翻译：激光打开加速器独立于偏置控制环路带宽
公开(公告)号：US07203213B2
公开(公告)日：2007-04-10
申请号：US10759987
申请日：2004-01-15
申请人： Douglas P. Anderson , Peter Chambers , Joseph J. Judkins, III , William Andrew Burkland
发明人： Douglas P. Anderson , Peter Chambers , Joseph J. Judkins, III , William Andrew Burkland
IPC分类号： H01S3/00
CPC分类号： H01S5/0683 , H01S5/0428 , H01S5/06825
摘要： An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.
摘要翻译：加速器电路被并入激光二极管系统中，用于加速激光二极管的导通操作，而与激光二极管系统的控制回路带宽无关。加速器电路在激光接通时向补偿电容器提供升压电流，补偿电容器用于建立激光二极管系统的控制回路带宽。升压电流使控制环能够快速增加激光二极管的偏置电流。当激光二极管达到所需的工作点时，升压电流终止，激光二极管系统的控制回路恢复正常的偏置电流控制。在一个实施例中，加速器电路包括控制电流源以实现开环开启控制的定时器电路。在另一个实施例中，加速器电路包括与单触发逻辑电路结合工作以提供闭环控制的比较器电路。

9. 发明授权

US07590890B2 Hot-swap power controller generating sequenced power-good signals 有权
标题翻译：热插拔功率控制器产生顺序的电源良好信号
公开(公告)号：US07590890B2
公开(公告)日：2009-09-15
申请号：US11466755
申请日：2006-08-23
申请人： William Andrew Burkland , Adolfo A. Garcia
发明人： William Andrew Burkland , Adolfo A. Garcia
IPC分类号： G06F11/00
CPC分类号： G06F13/4081
摘要： A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.
摘要翻译：这里描述了功率控制器系统，其中在系统上电时，功率良好信号（PWRGD）被断言，随后是略微延迟的功率良好信号（DLY_PWRGD）。该PWRGD信号表示向卡或其他设备提供良好的电力，并且延迟的信号告诉系统处理器现在可以与卡或其他设备进行通信。该延迟允许卡或其他设备在由功率控制器声明操作之前达到稳定状态。在关闭设备电源时，首先将DLY_PWRGD信号置为无效，并将电源从卡或其他设备中分离。然后PWRGD信号在短暂的延迟之后被断言。这种短暂的延迟允许卡内的电路通过例如执行停机程序来适当地关闭，使用卡中的存储电荷临时为卡供电。状态机用于执行四态上电和断电顺序。

10. 发明申请

US20080126814A1 Hot-Swap Power Controller Generating Sequenced Power-Good Signals 有权
标题翻译：热插拔功率控制器产生顺序的电源良好信号
公开(公告)号：US20080126814A1
公开(公告)日：2008-05-29
申请号：US11466755
申请日：2006-08-23
申请人： William Andrew Burkland , Adolfo A. Garcia
发明人： William Andrew Burkland , Adolfo A. Garcia
IPC分类号： G06F1/00
CPC分类号： G06F13/4081
摘要： A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.
摘要翻译：这里描述了功率控制器系统，其中在系统上电时，功率良好信号（PWRGD）被断言，随后是略微延迟的功率良好信号（DLY_PWRGD）。该PWRGD信号表示向卡或其他设备提供良好的电力，并且延迟的信号告诉系统处理器现在可以与卡或其他设备进行通信。该延迟允许卡或其他设备在由功率控制器声明操作之前达到稳定状态。在关闭设备电源时，首先将DLY_PWRGD信号置为无效，并将电源从卡或其他设备中分离。然后PWRGD信号在短暂的延迟之后被断言。这种短暂的延迟允许卡内的电路通过例如执行停机程序来适当地关闭，使用卡中的存储电荷临时为卡供电。状态机用于执行四态上电和断电顺序。

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