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1. 发明授权

US08195880B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow 有权
标题翻译：信息处理系统，具有双重缓存中的负载操作的即时调度，具有双重调度到写入/读取数据流
公开(公告)号：US08195880B2
公开(公告)日：2012-06-05
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

2. 发明授权

US08015358B2 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US08015358B2
公开(公告)日：2011-09-06
申请号：US12207393
申请日：2008-09-09
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。

3. 发明授权

US07987320B2 Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation 有权
标题翻译：缓存机制和方法，用于避免对不良受害者选择和回收受害者选择操作
公开(公告)号：US07987320B2
公开(公告)日：2011-07-26
申请号：US11951783
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/125 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

4. 发明授权

US07827354B2 Victim cache using direct intervention 失效
标题翻译：受害者缓存使用直接干预
公开(公告)号：US07827354B2
公开(公告)日：2010-11-02
申请号：US11923952
申请日：2007-10-25
申请人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
发明人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/127
摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.
摘要翻译：一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

5. 发明申请

US20100268880A1 Dynamic Runtime Modification of Array Layout for Offset 有权
标题翻译：用于偏移的阵列布局的动态运行时修改
公开(公告)号：US20100268880A1
公开(公告)日：2010-10-21
申请号：US12424348
申请日：2009-04-15
申请人： Ravi Kumar Arimilli , Donald W. Plass , William John Starke
发明人： Ravi Kumar Arimilli , Donald W. Plass , William John Starke
IPC分类号： G06F12/08 , G06F1/12
CPC分类号： G06F12/0886 , G06F9/30047 , G06F9/345
摘要： Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.
摘要翻译：公开了一种用于操作缓存系统的方法，系统和计算机程序产品。高速缓存系统可以包括多个高速缓存行，并且多条高速缓存行的第一高速缓存行可以包括多个高速缓存单元，以及耦合到多个高速缓存单元的总线。在一个或多个实施例中，总线可以包括可操作以接收第一控制信号并且将总线分为第一和第二部分或基于第一控制信号将总线聚合成整体的开关。当总线被分离时，多个高速缓存单元的第一高速缓存单元和第二高速缓存单元耦合到总线的相应的第一和第二部分。可以通过总线的各个部分选择来自第一和第二高速缓存单元的数据，并通过高速缓存系统的端口输出。

6. 发明申请

US20100262720A1 TECHNIQUES FOR WRITE-AFTER-WRITE ORDERING IN A COHERENCY MANAGED PROCESSOR SYSTEM THAT EMPLOYS A COMMAND PIPELINE 有权
标题翻译：在使用命令管道的协调管理处理器系统中进行写后写入的技术
公开(公告)号：US20100262720A1
公开(公告)日：2010-10-14
申请号：US12420889
申请日：2009-04-09
申请人： George William Daly, JR. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： George William Daly, JR. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
摘要翻译：用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。在这种情况下，通道标识符表示属于I / O流的I / O命令。命令位置指示符分配给每个I / O命令。命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

7. 发明授权

US07783841B2 Efficient coherency communication utilizing an IG coherency state 失效
标题翻译：使用IG一致性状态的高效一致性通信
公开(公告)号：US07783841B2
公开(公告)日：2010-08-24
申请号：US11836965
申请日：2007-08-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

8. 发明申请

US20090083489A1 L2 CACHE CONTROLLER WITH SLICE DIRECTORY AND UNIFIED CACHE STRUCTURE 失效
标题翻译： L2缓存控制器，具有SLICE DIRECTORY和统一的高速缓存结构
公开(公告)号：US20090083489A1
公开(公告)日：2009-03-26
申请号：US12325266
申请日：2008-12-01
申请人： Leo James Clark , James Stephen Fields, JR. , Guy Lynn Guthrie , William John Starke
发明人： Leo James Clark , James Stephen Fields, JR. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0851 , G06F12/0811
摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
摘要翻译：缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录使用控制单个访问/命令端口的单个缓存仲裁器进行管理。在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。

9. 发明申请

US20090031173A1 Method, Apparatus, and Computer Program Product in a Processor for Dynamically During Runtime Allocating Memory for In-Memory Hardware Tracing 有权
标题翻译：处理器中的方法，设备和计算机程序产品在运行时间内动态分配内存用于内存中硬件跟踪
公开(公告)号：US20090031173A1
公开(公告)日：2009-01-29
申请号：US12206967
申请日：2008-09-09
申请人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
发明人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/2268 , G06F11/3476 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.
摘要翻译：在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。处理器包含在数据处理系统中。处理器包括使用系统总线耦合在一起的多个处理单元。处理单元包括控制系统存储器的存储器控制器。确定存储跟踪数据所需的特定大小的系统存储器。硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。固件选择系统内存中的特定位置。所有特定位置在一起是特定的尺寸。固件分配由硬件跟踪设备专门使用的特定位置。

10. 发明授权

US07480772B2 Data processing system and method for efficient communication utilizing an Tn and Ten coherency states 有权
标题翻译：数据处理系统和利用Tn和10相关性状态的高效通信方法
公开(公告)号：US07480772B2
公开(公告)日：2009-01-20
申请号：US11835984
申请日：2007-08-08
申请人： James Stephen Fields, Jr. , Benjiman Lee Goodman , Guy Lynn Guthrie , William John Starke , Derek Edward Williams
发明人： James Stephen Fields, Jr. , Benjiman Lee Goodman , Guy Lynn Guthrie , William John Starke , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F12/084
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

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