专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140015569A1 FREQUENCY SYNTHESIZER TUNING 有权
标题翻译：频率合成器调谐
公开(公告)号：US20140015569A1
公开(公告)日：2014-01-16
申请号：US13546702
申请日：2012-07-11
申请人： William W. WALKER
发明人： William W. WALKER
IPC分类号： H03B21/00
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1243 , H03B2200/0048 , H03L7/0891 , H03L7/102 , H03L2207/06
摘要： A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal.
摘要翻译：频率合成器电路包括：相位确定器，被配置为基于输出信号和参考信号之间的相位差来输出相位差信号。频率合成器电路还可以包括在微调模式期间基于相位差信号和频带信号的值产生输出信号的压控振荡器。压电振荡器还可以在粗调谐模式期间被配置为基于电压和频带信号的值产生输出信号。频率合成器电路还可以包括被配置为产生频带信号的控制单元。在微调模式期间，频带信号的值可以是静态的，并且基于参考信号和输出信号之间的频率差在粗调谐模式期间改变。

2. 发明授权

US08618840B1 Frequency synthesizer tuning 有权
标题翻译：频率合成器调谐
公开(公告)号：US08618840B1
公开(公告)日：2013-12-31
申请号：US13546702
申请日：2012-07-11
申请人： William W. Walker
发明人： William W. Walker
IPC分类号： H03B21/00
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1243 , H03B2200/0048 , H03L7/0891 , H03L7/102 , H03L2207/06
摘要： A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal.
摘要翻译：频率合成器电路包括：相位确定器，被配置为基于输出信号和参考信号之间的相位差来输出相位差信号。频率合成器电路还可以包括在微调模式期间基于相位差信号和频带信号的值产生输出信号的压控振荡器。压电振荡器还可以在粗调谐模式期间被配置为基于电压和频带信号的值产生输出信号。频率合成器电路还可以包括被配置为产生频带信号的控制单元。在微调模式期间，频带信号的值可以是静态的，并且基于参考信号和输出信号之间的频率差在粗调谐模式期间改变。

3. 发明授权

US08300753B2 Triple loop clock and data recovery (CDR) 有权
标题翻译：三回路时钟和数据恢复（CDR）
公开(公告)号：US08300753B2
公开(公告)日：2012-10-30
申请号：US12510160
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0891 , H03L7/091 , H03L7/113 , H04L7/0004
摘要： In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.
摘要翻译：在一个实施例中，一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下，在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。

4. 发明申请

US20120177162A1 Symmetric Phase Detector 审中-公开
标题翻译：对称相位检测器
公开(公告)号：US20120177162A1
公开(公告)日：2012-07-12
申请号：US13424728
申请日：2012-03-20
申请人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
发明人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
IPC分类号： H04L27/06 , H03D13/00
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell.
摘要翻译：在一个实施例中，电路包括分别具有第一单元输入，第二单元输入和单元输出的第一混频器单元和第二混频器单元。电路包括被配置为接收具有第一相位的第一输入信号的第一电路输入。第一电路输入连接到第一混频器单元的第一单元输入和第二混频器单元的第二单元输入。电路包括第二电路输入，其配置为接收具有与第一相分离的第二相位的标称值的第二输入信号。第二电路输入连接到第一混频器单元的第二单元输入和第二混频器单元的第一单元输入。

5. 发明申请

US20100091927A1 Clock and Data Recovery (CDR) Using Phase Interpolation 有权
标题翻译：时钟和数据恢复（CDR）使用相位插值
公开(公告)号：US20100091927A1
公开(公告)日：2010-04-15
申请号：US12511365
申请日：2009-07-29
申请人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
发明人： William W. Walker , H. Anders Kristensson , Nikola Nedovic , Nestor Tzartzanis
IPC分类号： H04L27/01
CPC分类号： H03L7/091 , H03L7/087 , H03L7/0998
摘要： In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.
摘要翻译：在一个实施例中，电路包括被配置为产生k个第一时钟信号的压控振荡器（VCO），每个第一时钟信号各自具有基于电荷泵控制电压信号的第一相位; 配置成接收k个第一时钟信号的一个或多个相位内插器（PI）和一个或多个第一反馈控制信号并产生m个第二时钟信号，每个第二时钟信号基于k个第一时钟信号和一个或多个第一反馈控制信号; 第一相位检测器（PD），被配置为接收m个第二时钟信号，并且基于m个第二时钟信号产生一个或多个第一反馈控制信号; 配置为基于所述m个第二时钟信号产生一个或多个第二反馈控制信号的第二PD; 以及电荷泵，被配置为基于所述第二反馈控制信号输出所述电荷泵控制电压信号。

6. 发明申请

US20100091925A1 Triple Loop Clock and Data Recovery (CDR) 有权
标题翻译：三回路时钟和数据恢复（CDR）
公开(公告)号：US20100091925A1
公开(公告)日：2010-04-15
申请号：US12510160
申请日：2009-07-27
申请人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
发明人： Nikola Nedovic , Nestor Tzartzanis , William W. Walker
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/0891 , H03L7/091 , H03L7/113 , H04L7/0004
摘要： In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.
摘要翻译：在一个实施例中，一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下，在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。

7. 发明申请

US20100090723A1 Symmetric Phase Detector 失效
标题翻译：对称相位检测器
公开(公告)号：US20100090723A1
公开(公告)日：2010-04-15
申请号：US12511340
申请日：2009-07-29
申请人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
发明人： Nikola Nedovic , H. Anders Kristensson , William W. Walker
IPC分类号： H03D13/00
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.
摘要翻译：在一个实施例中，电路包括用于接收具有第一相位的第一输入信号的第一电路输入端; 用于接收具有第二相位的第二输入信号的第二电路输入; 用于输出电路输出信号的电路输出; 第一混频器单元，包括第一混频器单元输入，第二混频器单元输入和第一混频器单元输出; 以及包括第三混频器单元输入，第四混频器单元输入和第二混频器单元输出的第二混频器单元。第一电路输入连接到第一和第二混频器单元输入，第二电路输入连接到第二和第四混频器单元输入，并且组合第一和第二混频器单元输出以提供电路输出。电路输出信号的电流与第一和第二相之间的相位偏移成比例。

8. 发明授权

US07075842B2 Differential current-mode sensing methods and apparatuses for memories 失效
标题翻译：用于存储器的差分电流模式感测方法和装置
公开(公告)号：US07075842B2
公开(公告)日：2006-07-11
申请号：US10779464
申请日：2004-02-13
申请人： Nestor Tzartzanis , William W. Walker
发明人： Nestor Tzartzanis , William W. Walker
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C11/412 , G11C11/413
摘要： Disclosed is a memory architecture where current sense amplifiers are used instead of voltage sense amplifiers, and where the memory cells normally disposed along a single bit line are divided between two half bit lines. Each half bit line is coupled to a respective input of the current sense amplifier. When one of the memory cells is selected for reading, it couples a current related to its stored data state to the half bit line that it is coupled to. During this operation, a reference current is generated on the other half bit line. Also disclosed are novel current sense amplifiers.
摘要翻译：公开了一种存储架构，其中使用电流检测放大器来代替电压检测放大器，并且其中通常沿着单个位线布置的存储器单元被划分为两个半位线之间。每个半位线耦合到电流检测放大器的相应输入端。当选择其中一个存储单元进行读取时，它将与其存储的数据状态相关的电流与其耦合的半位线耦合。在该操作期间，在另一半位线上产生参考电流。还公开了新颖的电流检测放大器。

9. 发明授权

US06778466B2 Multi-port memory cell 有权
标题翻译：多端口存储单元
公开(公告)号：US06778466B2
公开(公告)日：2004-08-17
申请号：US10121968
申请日：2002-04-11
申请人： William W. Walker
发明人： William W. Walker
IPC分类号： G11C1304
CPC分类号： G11C8/16
摘要： An improved multi-port memory cell circuit which has a smaller number of write lines and/or transistors than conventional multi-port memory cells, and hence occupies a smaller area, is provided. The reduced area memory cell circuit includes: word lines associated with each bit line of a set of bit lines; a first word line for selecting a subset of the set of bit lines; a second word line for selecting a bit line of the subset of bit lines; and a memory cell for storing a bit value on the selected bit line.
摘要翻译：提供了一种改进的多端口存储单元电路，其具有比常规多端口存储器单元更少数量的写入线和/或晶体管，因此占据较小的面积。缩小面积存储单元电路包括：与一组位线的每个位线相关联的字线; 用于选择所述一组位线的子集的第一字线; 用于选择位线子集的位线的第二字线; 以及用于存储所选位线上的位值的存储单元。

10. 发明授权

US5987641A Wrist guards 失效
标题翻译：手腕卫兵
公开(公告)号：US5987641A
公开(公告)日：1999-11-23
申请号：US18977
申请日：1998-02-05
申请人： William W. Walker
发明人： William W. Walker
IPC分类号： A41D13/08 , A63B71/14
CPC分类号： A41D13/088 , A63B71/14 , A63B2209/10
摘要： A wrist pad is provided including a flexible removable wrap with a top extent and a bottom extent. At least one sleeve is mounted on the bottom extent of the wrap. A rigid element includes at least one portion defining a periphery of a cylinder and a sphere. Such rigid element is removably situated within the sleeve during use.
摘要翻译：提供了一种腕垫，其包括具有顶部范围和底部范围的柔性可移除的包裹物。至少一个套筒安装在包装的底部范围上。刚性元件包括限定圆柱体和球体的周边的至少一个部分。这种刚性元件在使用期间可移除地位于套筒内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式