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1. 发明授权

US09082751B2 Half-FinFET semiconductor device and related method 有权
标题翻译：半鳍FET半导体器件及相关方法
公开(公告)号：US09082751B2
公开(公告)日：2015-07-14
申请号：US13232737
申请日：2011-09-14
申请人： Xiangdong Chen , Wei Xia
发明人： Xiangdong Chen , Wei Xia
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L29/06
CPC分类号： H01L29/4236 , H01L29/0653 , H01L29/0692 , H01L29/66659 , H01L29/66787 , H01L29/7835 , H01L29/785
摘要： According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.
摘要翻译：根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域，从而导致半FinFET结构具有降低的导通电阻。

2. 发明授权

US09041171B2 Programmable interposer with conductive particles 有权
标题翻译：可编程插入式导电颗粒
公开(公告)号：US09041171B2
公开(公告)日：2015-05-26
申请号：US13340430
申请日：2011-12-29
申请人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： H01L21/326 , H01L23/495 , H05K1/11 , B82Y99/00 , H01L23/498 , H05K1/02 , H01L21/48 , H05K3/40
CPC分类号： H01L23/49827 , B82Y10/00 , H01L21/485 , H01L21/486 , H01L23/49822 , H01L2224/16225 , H05K1/029 , H05K3/4038 , H05K2201/0248 , H05K2201/026 , H05K2201/0323 , H05K2201/10378 , H05K2203/104 , H05K2203/105
摘要： An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.
摘要翻译：本公开的示例性实现包括具有顶部和底部接口电极和散布在可编程插值器内的导电粒子的可编程插值器。响应于将能量场施加到可编程内插器，导电颗粒能够在顶部和底部界面电极之间形成对准的构造，以便电连接顶部和底部界面电极。导电颗粒可具有导电外表面。此外，导电粒子可以是球形的。导电颗粒可以在可编程插入器中的界面层中的体积材料内，并且可以固化块状材料以确保顶部和底部界面电极之间的编程路径。

3. 发明授权

US08659081B2 Transistor with reduced channel length variation 有权
标题翻译：具有减小通道长度变化的晶体管
公开(公告)号：US08659081B2
公开(公告)日：2014-02-25
申请号：US13613864
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

4. 发明授权

US08493767B2 One-time programmable device having an LDMOS structure 有权
标题翻译：具有LDMOS结构的一次性可编程器件
公开(公告)号：US08493767B2
公开(公告)日：2013-07-23
申请号：US13252880
申请日：2011-10-04
申请人： Akira Ito , Xiangdong Chen
发明人： Akira Ito , Xiangdong Chen
IPC分类号： G11C17/00 , H01L23/52
CPC分类号： H01L29/7816 , H01L21/76224 , H01L23/5252 , H01L27/088 , H01L27/11206 , H01L27/11226 , H01L27/1124 , H01L27/11246 , H01L27/11266 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.
摘要翻译：根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门电极和编程栅极电介质。编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

5. 发明申请

US20130168854A1 Semiconductor Package with a Bridge Interposer 有权
标题翻译：具有桥插入器的半导体封装
公开(公告)号：US20130168854A1
公开(公告)日：2013-07-04
申请号：US13339266
申请日：2011-12-28
申请人： Sampath K.V. KARIKALAN , Sam Ziqun ZHAO , Kevin Kunzhong HU , Rezaur Rahman KHAN , Pieter VORENKAMP , Xiangdong CHEN
发明人： Sampath K.V. KARIKALAN , Sam Ziqun ZHAO , Kevin Kunzhong HU , Rezaur Rahman KHAN , Pieter VORENKAMP , Xiangdong CHEN
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L25/0655 , H01L23/48 , H01L23/49827 , H01L23/49833 , H01L23/538 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/80 , H01L24/82 , H01L25/0652 , H01L2224/0401 , H01L2224/05541 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73215 , H01L2224/73265 , H01L2224/96 , H01L2924/00014 , H01L2924/15192 , H01L2924/152 , H01L2924/1532 , H01L2924/30105 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).
摘要翻译：这里公开了包括桥插入器的半导体封装的各种实施方式。一个示例性实现包括具有位于桥插入件上方的第一部分的第一有源管芯和不位于桥插入件上的第二部分。半导体封装还包括具有位于桥插入件上方的第一部分的第二有源管芯和不位于桥插入件上的第二部分。第一有源裸片的第二部分和第二有源裸片的第二部分包括安装在封装衬底上的焊球，并且被配置为使用焊球将电信号传送到封装衬底，并且不使用贯穿半导体通孔（TSV ）。

6. 发明授权

US08455977B2 Programmable fuse 有权
标题翻译：可编程保险丝
公开(公告)号：US08455977B2
公开(公告)日：2013-06-04
申请号：US13466986
申请日：2012-05-08
申请人： Wei Xia , Xiangdong Chen , Akira Ito
发明人： Wei Xia , Xiangdong Chen , Akira Ito
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.
摘要翻译：根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属熔丝形成在栅极金属段的一部分中。该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

7. 发明申请

US20130105942A1 FINFET DEVICES 有权
标题翻译： FINFET器件
公开(公告)号：US20130105942A1
公开(公告)日：2013-05-02
申请号：US13287331
申请日：2011-11-02
申请人： Xiangdong Chen , Henry Chen , Agnes Woo , Wei Xia
发明人： Xiangdong Chen , Henry Chen , Agnes Woo , Wei Xia
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/785 , H01L28/20 , H01L29/66795 , H01L29/7855 , H01L29/7856 , H01L29/94
摘要： Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.
摘要翻译：公开了FinFET半导体器件的各种实施例。可以形成一对共用的源极，漏极和/或沟道的匹配电容器。因此，可以制造每个电容器的电容特性使得它们彼此相似。还描述了采用FinFET技术制造的电阻器。电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

8. 发明申请

US20130082347A1 One Time Programmable Structure Using a Gate Last High-K Metal Gate Process 有权
标题翻译：使用栅极最后的高K金属栅极工艺的一次性可编程结构
公开(公告)号：US20130082347A1
公开(公告)日：2013-04-04
申请号：US13249022
申请日：2011-09-29
申请人： Xiangdong CHEN , Wei Xia
发明人： Xiangdong CHEN , Wei Xia
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L27/0629 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.
摘要翻译：一种eFuse结构，其具有用作具有栅极的第一金属层，所述栅极包括未经掺杂的多晶硅（poly），第二金属层和高K电介质层，所述第一金属层全部用浅沟槽隔离层形成在硅衬底上，以及工艺提供制造相同的。 eFuse结构使得能够使用少量的电流来熔断熔丝，从而允许使用更小的MOSFET。

9. 发明申请

US20130082325A1 One-Time Programmable Device Having an LDMOS Structure and Related Method 有权
标题翻译：具有LDMOS结构和相关方法的一次性可编程器件
公开(公告)号：US20130082325A1
公开(公告)日：2013-04-04
申请号：US13252880
申请日：2011-10-04
申请人： Akira Ito , Xiangdong Chen
发明人： Akira Ito , Xiangdong Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/76224 , H01L23/5252 , H01L27/088 , H01L27/11206 , H01L27/11226 , H01L27/1124 , H01L27/11246 , H01L27/11266 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66681 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.
摘要翻译：根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门电极和编程栅极电介质。编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

10. 发明申请

US20130001687A1 Transistor with Reduced Channel Length Variation 有权
标题翻译：具有减少通道长度变化的晶体管
公开(公告)号：US20130001687A1
公开(公告)日：2013-01-03
申请号：US13613864
申请日：2012-09-13
申请人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Wei Xia , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

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