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    • 1. 发明授权
    • Multiple patterning lithography using spacer and self-aligned assist patterns
    • 使用间隔物和自对准辅助图案进行多重图案化光刻
    • US08629064B2
    • 2014-01-14
    • US13167681
    • 2011-06-23
    • Xiaoyang LiDuan-Fu Stephen Hsu
    • Xiaoyang LiDuan-Fu Stephen Hsu
    • H01L21/311
    • G03F1/36G03F7/70466G03F7/70633
    • The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.
    • 本发明涉及光刻设备和工艺,更具体地涉及用于将目标图案打印超出光刻设备的分辨率限制的多重图形化光刻技术。 自对准辅助图案(SAP)以原始设计布局从自动化方式导出,使用基于某些预定义设计规则的几何布尔运算,并且包括在掩模布局中以用于目标图案的各种子布局的有效自对准 在多重图案化光刻工艺期间。 SAP可以具有任何形状和尺寸,并且可以具有连续特征(例如,环)或不连续的(例如,彼此不连接的条)特征。 使用间隔物和SAP的端到端多重图案化光刻可以使用正色调光刻,和/或负色调光刻用于线和/或空间印刷。
    • 2. 发明申请
    • Multiple Patterning Lithography Using Spacer and Self-Aligned Assist Patterns
    • 使用间隔和自对准辅助模式进行多重图案化光刻
    • US20110318927A1
    • 2011-12-29
    • US13167681
    • 2011-06-23
    • Xiaoyang LiDuan-Fu Stephen Hsu
    • Xiaoyang LiDuan-Fu Stephen Hsu
    • H01L21/306G06F17/50
    • G03F1/36G03F7/70466G03F7/70633
    • The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.
    • 本发明涉及光刻设备和工艺,更具体地涉及用于将目标图案打印超出光刻设备的分辨率限制的多重图形化光刻技术。 自对准辅助图案(SAP)以原始设计布局从自动化方式导出,使用基于某些预定义设计规则的几何布尔运算,并且包括在掩模布局中以用于目标图案的各种子布局的有效自对准 在多重图案化光刻工艺期间。 SAP可以具有任何形状和尺寸,并且可以具有连续特征(例如,环)或不连续的(例如,彼此不连接的条)特征。 使用间隔物和SAP的端到端多重图案化光刻可以使用正色调光刻,和/或负色调光刻用于线和/或空间印刷。
    • 3. 发明授权
    • Lithography process modeling of asymmetric patterns
    • 非对称图案的平版印刷过程建模
    • US07149998B2
    • 2006-12-12
    • US10335513
    • 2002-12-30
    • Xiaoyang Li
    • Xiaoyang Li
    • G06F17/50
    • G03F1/68G03F1/26
    • A lithography process model is generated to account for asymmetric printing of a feature of a target pattern to help better predict how the target pattern will print. The process model for one embodiment may be generated based on data generated from measurements of spacings between symmetrically defined features of printed test patterns to help predict edge offsets of the feature relative to the target pattern when printed and/or to help predict a dimension of the feature when printed. The process model may be used to help design, manufacture, and/or inspect a mask to help print the target pattern more accurately and therefore help manufacture an integrated circuit (IC), for example, that more accurately matches its intended layout.
    • 生成光刻过程模型以解决目标图案的特征的不对称打印,以帮助更好地预测目标图案将如何打印。 一个实施例的过程模型可以基于由打印测试图案的对称定义的特征之间的间隔的测量产生的数据来产生,以帮助预测当打印时相对于目标图案的特征的边缘偏移和/或帮助预测 功能打印时。 过程模型可用于帮助设计,制造和/或检查掩模以帮助更准确地印刷目标图案,并且因此有助于制造例如更准确地匹配其预期布局的集成电路(IC)。