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    • 2. 发明授权
    • Failsafe ESD protection
    • 防止ESD保护
    • US09124086B2
    • 2015-09-01
    • US13557520
    • 2012-07-25
    • Wei Yu MaKuo-Ji Chen
    • Wei Yu MaKuo-Ji Chen
    • H02H9/04
    • H02H9/04H02H9/046
    • Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.
    • 提供了一种或多种用于提供故障安全静电放电(ESD)保护的技术和/或系统。 在一个实施例中,通过将电压故障安全(VFS)电源电压连接到NWELL电路接口(例如PMOS晶体管)并将PAD连接到VFS或NWELL电路接口中的至少一个来提供ESD保护。 为此,要保护免受ESD(例如,可操作地连接到PAD的电路)的电路具有故障安全ESD保护(例如,使得可以使用非快速恢复的NMOS器件来放电ESD电流,其中非快速恢复NMOS 通常消耗更少的半导体不动产,并且与快速恢复NMOS相比,生产的复杂度较低)。 以这种方式,有效地提供故障安全ESD保护。