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1. 发明申请

US20130001772A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130001772A1
公开(公告)日：2013-01-03
申请号：US13607766
申请日：2012-09-09
申请人： Yuki KOIDE , Masataka MINAMI
发明人： Yuki KOIDE , Masataka MINAMI
IPC分类号： H01L23/498
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/522 , H01L23/525 , H01L24/05 , H01L2224/0231 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13099 , H01L2224/13111 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
摘要翻译：一种半导体器件，其具有WPP技术中的再分配互连和改善的可靠性，其中再分配互连具有在半导体衬底的平面内彼此电分离的第一图案和第二图案，第一图案电耦合到多层互连并且浮置的第二图案在半导体衬底的平面内共存，并且半导体衬底的平面内的第一图案和第二图案的总和占据比例，即再分布互连的占有率为35 至60％。

2. 发明申请

US20090206490A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAE 有权
标题翻译：半导体器件和制造SAE的方法
公开(公告)号：US20090206490A1
公开(公告)日：2009-08-20
申请号：US12352591
申请日：2009-01-12
申请人： Yuki KOIDE , Masataka Minami
发明人： Yuki KOIDE , Masataka Minami
IPC分类号： H01L23/538 , G06F17/50 , H01L21/768
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/522 , H01L23/525 , H01L24/05 , H01L2224/0231 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13099 , H01L2224/13111 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
摘要翻译：一种半导体器件，其具有WPP技术中的再分配互连和改善的可靠性，其中再分配互连具有在半导体衬底的平面内彼此电分离的第一图案和第二图案，第一图案电耦合到多层互连并且浮置的第二图案在半导体衬底的平面内共存，并且半导体衬底的平面内的第一图案和第二图案的总和占据比例，即再分布互连的占有率为35 至60％。

3. 发明授权

US08492847B2 Semiconductor device having insulating film with increased tensile stress and manufacturing method thereof 有权
标题翻译：具有拉伸应力增加的绝缘膜的半导体装置及其制造方法
公开(公告)号：US08492847B2
公开(公告)日：2013-07-23
申请号：US13341421
申请日：2011-12-30
申请人： Tatsunori Murata , Yuki Koide
发明人： Tatsunori Murata , Yuki Koide
IPC分类号： H01L21/70 , H01L21/4763
CPC分类号： H01L29/7843 , H01L21/2686 , H01L21/28518 , H01L21/76802 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Over a semiconductor substrate, a silicon nitride film is formed so as to cover n-channel MISFETs. The silicon nitride film is a laminate film which may be made of first, second, and third silicon nitride films. The total film thickness of the first and second silicon nitride films is smaller than half a spacing between a first sidewall spacer and a second sidewall spacer. After being deposited, the first and second silicon nitride films are subjected to treatments to have increased tensile stresses. The total film thickness of the first, second, and third silicon nitride films is not less than half the spacing between the first and second sidewall spacers. The third silicon nitride film is not subjected to any tensile-stress-increasing treatment, or may be subjected to a lesser amount of such treatment.
摘要翻译：在半导体衬底上形成氮化硅膜以覆盖n沟道MISFET。氮化硅膜是可由第一，第二和第三氮化硅膜制成的层压膜。第一和第二氮化硅膜的总膜厚度小于第一侧壁间隔物和第二侧壁间隔物之间的间隔的一半。沉积后，对第一和第二氮化硅膜进行处理以增加拉伸应力。第一，第二和第三氮化硅膜的总膜厚度不小于第一和第二侧壁间隔物之间的间距的一半。第三氮化硅膜不经受任何拉伸应力增加处理，或者可以进行较少量的这种处理。

4. 发明授权

US07977183B2 Semiconductor device and method of manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07977183B2
公开(公告)日：2011-07-12
申请号：US12605328
申请日：2009-10-24
申请人： Yuki Koide
发明人： Yuki Koide
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L29/7843
摘要： To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced.The technical idea of the present invention lies in the configuration in which in a first to a third silicon nitride film to be formed by lamination, the respective film thicknesses thereof are not constant but become smaller in order from the third silicon nitride film in the upper layer to the first silicon nitride film in the lower layer while the total film thickness thereof is kept constant. Due to this it is possible to improve the embedding characteristic of the third silicon nitride film in the uppermost layer in particular, while ensuring the tensile stress of the first to third silicon nitride films, which makes effective the strained silicon technique.
摘要翻译：为了提供能够提高半导体装置的可靠性的技术，即使其小型化也是前进的。本发明的技术思想在于，在通过层叠形成的第一至第三氮化硅膜中，其各自的膜厚度不是恒定的，而是从上部的第三氮化硅膜的顺序变小层到下层中的第一氮化硅膜，而其总膜厚度保持恒定。由此，可以在确保第一至第三氮化硅膜的拉伸应力的同时，特别提高最上层的第三氮化硅膜的嵌入特性，这使得应变硅技术变得有效。

5. 发明申请

US20120199913A1 Semiconductor Device Having Insulating Film With Increased Tensile Stress and Manufacturing Method Thereof 有权
标题翻译：具有增加拉伸应力的绝缘膜的半导体器件及其制造方法
公开(公告)号：US20120199913A1
公开(公告)日：2012-08-09
申请号：US13341421
申请日：2011-12-30
申请人： Tatsunori Murata , Yuki Koide
发明人： Tatsunori Murata , Yuki Koide
IPC分类号： H01L27/092 , H01L21/28 , H01L27/088
CPC分类号： H01L29/7843 , H01L21/2686 , H01L21/28518 , H01L21/76802 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Over a semiconductor substrate, a silicon nitride film is formed so as to cover n-channel MISFETs. The silicon nitride film is a laminate film which may be made of first, second, and third silicon nitride films. The total film thickness of the first and second silicon nitride films is smaller than half a spacing between a first sidewall spacer and a second sidewall spacer. After being deposited, the first and second silicon nitride films are subjected to treatments to have increased tensile stresses. The total film thickness of the first, second, and third silicon nitride films is not less than half the spacing between the first and second sidewall spacers. The third silicon nitride film is not subjected to any tensile-stress-increasing treatment, or may be subjected to a lesser amount of such treatment.
摘要翻译：在半导体衬底上形成氮化硅膜以覆盖n沟道MISFET。氮化硅膜是可由第一，第二和第三氮化硅膜制成的层压膜。第一和第二氮化硅膜的总膜厚度小于第一侧壁间隔物和第二侧壁间隔物之间的间隔的一半。沉积后，对第一和第二氮化硅膜进行处理以增加拉伸应力。第一，第二和第三氮化硅膜的总膜厚度不小于第一和第二侧壁间隔物之间的间距的一半。第三氮化硅膜不经受任何拉伸应力增加处理，或者可以进行较少量的这种处理。

6. 发明授权

US07939925B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07939925B2
公开(公告)日：2011-05-10
申请号：US12258067
申请日：2008-10-24
申请人： Yuki Koide , Kouichi Meguro
发明人： Yuki Koide , Kouichi Meguro
IPC分类号： H01L23/52
CPC分类号： H01L21/568 , H01L21/561 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48095 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/85001 , H01L2224/854 , H01L2224/85951 , H01L2224/97 , H01L2225/0651 , H01L2225/06575 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/351 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/4554
摘要： A semiconductor package having a molding unit that seals bonding wires connected to electrode pads of a semiconductor chip is provided with through electrode units comprising bonding wires embedded therein and penetrating the molding unit. A leading end of the respective through electrode units is exposed from an upper surface of the molding unit and a lower surface of the molding unit.
摘要翻译：具有密封与半导体芯片的电极焊盘连接的接合线的成型单元的半导体封装设置有贯通电极单元，该电极单元包括嵌入其中并穿透成型单元的接合线。各贯通电极单元的前端从模制单元的上表面和模制单元的下表面露出。

7. 发明申请

US20100117158A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100117158A1
公开(公告)日：2010-05-13
申请号：US12605328
申请日：2009-10-24
申请人： Yuki KOIDE
发明人： Yuki KOIDE
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced.The technical idea of the present invention lies in the configuration in which in a first to a third silicon nitride film to be formed by lamination, the respective film thicknesses thereof are not constant but become smaller in order from the third silicon nitride film in the upper layer to the first silicon nitride film in the lower layer while the total film thickness thereof is kept constant. Due to this it is possible to improve the embedding characteristic of the third silicon nitride film in the uppermost layer in particular, while ensuring the tensile stress of the first to third silicon nitride films, which makes effective the strained silicon technique.
摘要翻译：为了提供能够提高半导体装置的可靠性的技术，即使其小型化也是前进的。本发明的技术思想在于，在通过层叠形成的第一至第三氮化硅膜中，其各自的膜厚度不是恒定的，而是从上部的第三氮化硅膜的顺序变小层到下层中的第一氮化硅膜，而其总膜厚度保持恒定。由此，可以在确保第一至第三氮化硅膜的拉伸应力的同时，特别提高最上层的第三氮化硅膜的嵌入特性，这使得应变硅技术变得有效。

8. 发明申请

US20090267207A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090267207A1
公开(公告)日：2009-10-29
申请号：US12258067
申请日：2008-10-24
申请人： Yuki Koide , Kouichi Meguro
发明人： Yuki Koide , Kouichi Meguro
IPC分类号： H01L23/52 , H01L23/48 , H01L21/56 , H01L21/768
CPC分类号： H01L21/568 , H01L21/561 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48095 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/85001 , H01L2224/854 , H01L2224/85951 , H01L2224/97 , H01L2225/0651 , H01L2225/06575 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/351 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/4554
摘要： A semiconductor package having a molding unit that seals bonding wires connected to electrode pads of a semiconductor chip is provided with through electrode units comprising bonding wires embedded therein and penetrating the molding unit. A leading end of the respective through electrode units is exposed from an upper surface of the molding unit and a lower surface of the molding unit.
摘要翻译：具有密封与半导体芯片的电极焊盘连接的接合线的成型单元的半导体封装设置有贯通电极单元，该电极单元包括嵌入其中并穿透成型单元的接合线。各贯通电极单元的前端从模制单元的上表面和模制单元的下表面露出。

9. 发明授权

US08274157B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08274157B2
公开(公告)日：2012-09-25
申请号：US12883278
申请日：2010-09-16
申请人： Yuki Koide , Masataka Minami
发明人： Yuki Koide , Masataka Minami
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/522 , H01L23/525 , H01L24/05 , H01L2224/0231 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13099 , H01L2224/13111 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
摘要翻译：一种半导体器件，其具有WPP技术中的再分配互连和改善的可靠性，其中再分配互连具有在半导体衬底的平面内彼此电分离的第一图案和第二图案，第一图案电耦合到多层互连并且浮置的第二图案在半导体衬底的平面内共存，并且半导体衬底的平面内的第一图案和第二图案的总和占据比例，即再分布互连的占有率为35 至60％。

10. 发明申请

US20110260256A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260256A1
公开(公告)日：2011-10-27
申请号：US13175819
申请日：2011-07-01
申请人： YUKI KOIDE
发明人： YUKI KOIDE
IPC分类号： H01L27/088
CPC分类号： H01L21/823807 , H01L29/7843
摘要： To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced.The technical idea of the present invention lies in the configuration in which in a first to a third silicon nitride film to be formed by lamination, the respective film thicknesses thereof are not constant but become smaller in order from the third silicon nitride film in the upper layer to the first silicon nitride film in the lower layer while the total film thickness thereof is kept constant. Due to this it is possible to improve the embedding characteristic of the third silicon nitride film in the uppermost layer in particular, while ensuring the tensile stress of the first to third silicon nitride films, which makes effective the strained silicon technique.
摘要翻译：为了提供能够提高半导体装置的可靠性的技术，即使其小型化也是前进的。本发明的技术思想在于，在通过层叠形成的第一至第三氮化硅膜中，其各自的膜厚度不是恒定的，而是从上部的第三氮化硅膜的顺序变小层到下层中的第一氮化硅膜，而其总膜厚度保持恒定。由此，可以在确保第一至第三氮化硅膜的拉伸应力的同时，特别提高最上层的第三氮化硅膜的嵌入特性，这使得应变硅技术变得有效。

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